Ultra high speed Full Adders

IEICE Electronics Express

Volumn 5, Issue 18, 2008, Pages 744-749

  Navi, K ^a   Mirzaee, R Faghih ^a   Moaiyeri, M H ^a   Nezhad, B Mazloom ^a   Hashemipour, O ^a   Shams, K ^a  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

Full Adder cell; High speed; Low voltage; Majority function

Indexed keywords

CELLS; CYTOLOGY; PROBABILITY DENSITY FUNCTION; SPEED;

DELAY PRODUCTS; FULL ADDER CELL; FULL ADDERS; HIGH SPEED; INPUT PATTERNS; LOW VOLTAGE; LOW VOLTAGES; MAJORITY FUNCTION; MAJORITY FUNCTIONS; POWER CONSUMPTION PARAMETERS; ULTRA HIGHS;

ADDERS;

EID: 54249143648     PISSN: None     EISSN: 13492543     Source Type: Journal    
DOI: 10.1587/elex.5.744     Document Type: Article

References (5)

1. R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.
2. rd International Symposium on Image and Signal Processing and Analysis (ISPA), vol. 1, pp. 454-458, Sept. 2003.
3. V. Foroutan, K. Navi, and M. Haghparast, "A new low power dynamic full adder cell based on majority function," World Applied Sciences Journal, vol. 4, no. 1, pp. 133-141, 2008.
4. K. Navi, O. Kavehie, M. Ruholamini, A. Sahafi, S. Mehrabi, and N. Dadkhahi, "Low-power and high-performance 1-bit CMOS Full Adder cell," JCP, Journal of Computers, vol. 3, pp. 48-54, Feb. 2008.
5. S. Heo and K. Asanovic, "Leakage-biased domino circuits for dynamic fine-grain leakage reduction," Symposium on VLSI Circuits, pp. 316-319, June 2002.