Circuit techniques for CMOS low-power high-performance multipliers

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 10, 1996, Pages 1535-1546

  Abu Khater, Issam S ^a,b,c,e,f   Bellaouar, Abdellatif ^b,d,g,h   Elmasry, M I ^a,b  

^a IEEE

^b UNIVERSITY OF WATERLOO   (Canada)

^c INTEL CORPORATION   (United States)

^d TEXAS INSTRUMENTS   (United States)

^e DALHOUSIE UNIVERSITY   (Canada)

^f LUCENT TECHNOLOGIES   (United States)

^g UNIVERSITÉ DE TOULOUSE   (France)

^h HCR Research Center   (Algeria)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; MULTIPLYING CIRCUITS; OPTIMIZATION; VLSI CIRCUITS;

BOOTH ALGORITHM; COMPLEMENTARY PASS TRANSISTOR LOGIC TRANSMISSION GATE;

CMOS INTEGRATED CIRCUITS;

EID: 0030269438     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.540066     Document Type: Article

References (13)

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