A content aware integer register file organization

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 314-324

  González, Rubén ^a   Cristal, Adrián ^a   Ortega, Daniel ^b   Veidenbaum, Alexander ^c   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHING; INTEGER REGISTER; MEMORY ADDRESSES; PARTIAL VALUE LOCALITY;

APPROXIMATION THEORY; COMPUTER SYSTEMS; ENERGY UTILIZATION; FILE ORGANIZATION; NATURAL FREQUENCIES; OPTIMIZATION; VIRTUAL REALITY;

PROGRAM PROCESSORS;

EID: 4644295620     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. A. González, J. González, and M. Valero. Virtual-physical registers. In Intl. Symposium on High-Performance Computer Architecture, February 1998.
2. A. Seznec, E. Toullec, and O. Rochecouste. Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. In Intl. symposium on Microarchitecture, 2002.
3. A J. Smith. Cache memories. In ACM Computing Surveys (CSUR), pages 473-530. ACM Press, 1982.
4. Emer. Ev8: The post-ultimate alpha. In Keynote speech at the Intl. Conference on Parallel Architectures and Compilation Techniques, September 2001.
5. I. Park, M. Powell and T. Vijaykumar. Reducing register ports for higher speed and lower energy. In 35th intl. symposium on Microarchitecture, 2002.
6. J. Lo, S. Parekh, S. Eggers, H. Levy, and D. Tullsen. Software-directed register deallocation for simultaneous multithreaded processors. Technical Report TR-97-12-01, University of Washington, Department of Computer Science and Engineering, 1997.
7. J. Tseng and K. Asanović. Energy-efficient register access. In 13th Symposium on Integrated Circuits and Systems Design (SBCCT00), September 2000.
8. J. F. Martinez, J. Renau, M.C. Huang, M. Prvulovic, and J. Torrellas. Cherry: checkpointed early resource recycling in out-of-order microprocessors. In 35th intl. symposium on Microarchitecture, 2002.
9. J. S. Lee, W.-K. Hong, and S.-D. Kim. Design and evaluation of a selective compressed memory system. In Intl. Conference on 26 Computer Design (ICCD '99), October 1999. IEEE.
10. J. H. Tseng, Krste Asanović. Banked multiported register files for high-frequency superscalar microprocessors. In 30th intl. symposium on Computer architecture, June 2003.
11. J. L. Cruz, A. González, M. Valero, and N. P. Topham. Multiple-banked register file architectures. In 27th Intl. Symposium on Computer Architecture, 2000.
12. L. Villa, M. Zhang, and K. Asanović. Dynamic zero compression for cache energy reduction. In 33rd annual intl. symposium on Microarchitecture, 2000.
13. M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In 26th annual intl. symposium on Microarchitecture, 1993.
14. M. H. Lipasti and J.P. Shen. Exceeding the dataow limit via value prediction. In. 29th annual Intl. symposium on Microarchitecture, 1996.
15. th Intl. Conference on Supercomputing. June 2003.
16. R. Balasubramonian, S. Dwarkadas, and D. Albonesi. Dynamically allocating processor resources between nearby and distant ilp. In 28th Intl. symposium on Computer Architecture, 2001.
17. R. Canal, A. González, and J.E. Smith. Very low energy pipelines using significance compression. In 33rd Intl. symposium on Microarchitecture, 2000.
18. S. Balakrishnan and G. Sohi. Exploiting value locality in physical register files. Research report, University of Wisconsin, 2002.
19. S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz. A novel renaming scheme to exploit value temporal locality through physical register reuse and unification. In 31st Intl. symposium on Microarchitecture, 1998.
20. S. Rixner, W. Dally, B. Khailany, P. Mattson, U. Kapasi, and J. Owens. Register organization for media processing. In Sixth Intl. Symposium on High-Performance Computer Architecture, January 1999.
21. T. B. Smith, B. Abali, D. E. Po_, and R. B. Tremaine. Memory expansion technology (mxt): Competitive impact. March 2001.
22. T. Monreal, V. Vinals, A. González, and M. Valero. Hardware schemes for early register release. In Intl. Conference on Parallel Processing, 2002.
23. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In Intl. Conference on Parallel Architectures and Compilation Techniques, 2001.
24. V. Zyuban and P. Kogge. The energy complexity of register files. In Intl. symposium on Low energy electronics and design, 1998.
25. Y. Zhang, J. Yang, and R. Gupta. Frequent value locality and value centric data cache design. In ninth Intl. conference on Architectural support for programming languages and operating systems, 2000.