Improving soft-error tolerance of FPGA configuration bits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 107-110

  Srinivasan, Suresh ^a   Gayasen, Aman ^a   Vijaykrishnan, N ^a   Kandemir, M ^a   Xie, Y ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYMMETRIC SRAM (ASRAM); CIRCUIT NODES; SILICON SUBSTRATES; SOFT ERRORS;

AMPLIFIERS (ELECTRONIC); CAPACITANCE; ERROR ANALYSIS; LEAKAGE CURRENTS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 16244396731     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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