Analytical semi-empirical model for ser sensitivity estimation of deep-submicron CMOS circuits

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 3-8

  Heijmen, Tino ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; NEUTRONS; PRODUCT DESIGN; SENSITIVITY ANALYSIS;

CIRCUIT SIMULATIONS; DEEP-SUBMICRON CMOS TECHNOLOGIES; DESIGN MODIFICATIONS; SOFT-ERROR RATE (SER);

CMOS INTEGRATED CIRCUITS;

EID: 28044464102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.15     Document Type: Conference Paper

References (13)

1. R. Baumann. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction. In IEDM Tech. Dig., pages 329-332, 2002.
2. L. Freeman. Critical charge calculations for a bipolar SRAM array. IBM J. Research and Development, 40(1):119-129, Jan. 1996.
3. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta, and C. Dai. Impact of CMOS process scaling and SOI on the soft error rates of logic processes. In Proc. VLSI Tech. Dig., pages 73-74, 2001.
4. P. Hazucha, T. Karnik, J. Maiz, S. Walsta, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, and S. Borkar. Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation. In IEDM Tech. Dig., pages 523-526, 2003.
5. P. Hazucha and C. Svensson. Cosmic ray soft error rate characterization of a standard 0.6-μm CMOS process. IEEE J. Solid-State Circuits, 35(10):1422-1429, Oct. 2000.
6. T. Heijmen and B. Kruseman. Impact of process variations on the alpha-particle-induced SER of embedded SRAMs. In Proc. Int'l Conf. Memory Technology and Design, 2005. Accepted for publication.
7. T. Heijmen, B. Kruseman, R. van Veen, and M. Meijer. Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs. In Proc. IEEE Int'l Reliability Physics Symp., pages 675-676, 2004.
8. JESD89. Measurement and reporting of alpha particles and terrestrial cosmic ray-induced soft errors in semiconductor devices, Aug. 2001.
9. A. Nieuwland and P. Gindner. Automated logic SER analysis and on-line SER reduction. In Proc. IEEE Int'l On-line Testing Symp., page 177, 2004.
10. P. Roche, G. Gasiot, K. Forbes, V. O'Sullivan, and V. Ferlet. Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node. IEEE Trans. Nuclear Science, 50(6):2046-2054, Dec. 2003.
11. N. Seifert, X. Zhu, and L. Massengill. Impact of scaling on soft-error rates in commercial microprocessors. IEEE Trans. Nuclear Science, 49(6):3100-3106, Dec. 2002.
12. N. Seifert, X. Zhu, D. Moyer, R. Mueller, R. Hokinson, N. Leland, M. Shade, and L. Massengill. Frequency dependence of soft error rates for sub-micron CMOS technologies. In IEDM Tech. Dig., pages 323-326, 2001.
13. G. Srinivasan. Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview. IBM J. Research and Development, 40(1):77-89, Jan. 1996.