Soft error rate reduction using redundancy addition and removal

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 559-564

  Wu, Kai Chiang ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT RELIABILITY; CURRENT TECHNOLOGIES; DESIGN AUTOMATION CONFERENCE; FAILURE PROBABILITIES; LOW AREA; RELIABILITY DEGRADATION; SHRINKING FEATURE SIZES; SOFT ERROR RATES; SOFT ERRORS; SOFT-ERROR RATE; SOUTH PACIFIC; SUPPLY VOLTAGES; TRANSIENT FAULTS;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ERROR ANALYSIS; ERRORS; INDUSTRIAL ENGINEERING; LEARNING SYSTEMS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); QUALITY ASSURANCE; REDUNDANCY; RELIABILITY; SULFATE MINERALS; SWITCHING CIRCUITS; SWITCHING THEORY;

ERROR CORRECTION;

EID: 49549090838     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4484014     Document Type: Conference Paper

References (14)

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