Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to lOnm and 30nm gate length

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 59-62

  Collaert, N ^a   Von Arnim, K ^b   Rooyackers, R ^a   Vandeweyer, T ^a   Mercha, A ^a   Parvais, B ^a   Witters, L ^a   Nackaerts, A ^d   Sanchez, E Altamirano ^a   Demand, M ^a   Hikavyy, A ^a   Demuynck, S ^a   Devriendt, K ^a   Bauer, F ^b   Ferain, I ^c   Veloso, A ^a   De Meyer, K ^a   Biesemans, S ^a   Jurczak, M ^a  

^a IMEC   (Belgium)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d NXP TSMC Research Center   (Belgium)

Author keywords

Ring oscillators; SOI FinFET; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; LSI CIRCUITS; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

DEVICE DIMENSIONS; FIN WIDTHS; FINFETS; GA TE LENGTHS; GATE STACKS; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; LARGE-SCALE INTEGRATION; LOW VOLTAGES; PERFORMANCE DATA; RING OSCILLATORS; SOI FINFET; SRAM; SRAM CELLS;

INTEGRATED CIRCUITS;

EID: 51849135409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567246     Document Type: Conference Paper

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