메뉴 건너뛰기




Volumn 56, Issue 2, 2009, Pages 284-290

A comprehensive investigation of analog performance for uniaxial strained PMOSFETs

Author keywords

CMOS; DC gain; Device mismatch; Linearity; Low frequency noise; Process induced strain; Transconductance to drain current ratio; Uniaxial strained PMOSFET

Indexed keywords

CARRIER MOBILITY; LINEARIZATION; MOS DEVICES; MOSFET DEVICES; THERMAL NOISE; TRANSCONDUCTANCE;

EID: 59849101588     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2010590     Document Type: Article
Times cited : (9)

References (36)
  • 1
    • 4544324636 scopus 로고    scopus 로고
    • Device challenges and opportunities
    • C. Hu, "Device challenges and opportunities," in VLSI Symp. Tech. Dig., 2004, pp. 4-5.
    • (2004) VLSI Symp. Tech. Dig , pp. 4-5
    • Hu, C.1
  • 3
    • 46049083423 scopus 로고    scopus 로고
    • Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima, High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates, in IEDM Tech. Dig., 2006, pp. 1-4.
    • Y. Tateshita, J. Wang, K. Nagano, T. Hirano, Y. Miyanami, T. Ikuta, T. Kataoka, Y. Kikuchi, S. Yamaguchi, T. Ando, K. Tai, R. Matsumoto, S. Fujita, C. Yamane, R. Yamamoto, S. Kanda, K. Kugimiya, T. Kimura, T. Ohchi, Y. Yamamoto, Y. Nagahama, Y. Hagimoto, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Kadomura, and N. Nagashima, "High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates," in IEDM Tech. Dig., 2006, pp. 1-4.
  • 6
    • 20544447617 scopus 로고    scopus 로고
    • Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs
    • S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., 2004, pp. 221-227.
    • (2004) IEDM Tech. Dig , pp. 221-227
    • Thompson, S.E.1    Sun, G.2    Wu, K.3    Lim, J.4    Nishida, T.5
  • 7
    • 33646043420 scopus 로고    scopus 로고
    • Uniaxial-process-induced strained-Si: Extending the CMOS roadmap
    • May
    • S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, "Uniaxial-process-induced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
    • (2006) IEEE Trans. Electron Devices , vol.53 , Issue.5 , pp. 1010-1020
    • Thompson, S.E.1    Sun, G.2    Choi, Y.S.3    Nishida, T.4
  • 8
    • 34447264710 scopus 로고    scopus 로고
    • X. Chen, S. Fang, W. Gao, T. Dyer, Y. W. Teh, S. S. Tan, Y. Ko, C. Baiocco, A. Ajmera, J. Park, J. Kim, R. Stierstorfer, D. Chidambarrao, Z. Luo, N. Nivo, P. Nguyen, J. Yuan, S. Panda, O. Kwon, N. Edleman, T. Tjoa, J. Widodo, M. Belyansky, M. Sherony, R. Amos, H. Ng, M. Hierlemann, D. Coolbough, A. Steegen, I. Yang, J. Sudijono, T. Schiml, J. H. Ku, and C. Davis, Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond, in VLSI Symp. Tech. Dig., 2006, pp. 60-61.
    • X. Chen, S. Fang, W. Gao, T. Dyer, Y. W. Teh, S. S. Tan, Y. Ko, C. Baiocco, A. Ajmera, J. Park, J. Kim, R. Stierstorfer, D. Chidambarrao, Z. Luo, N. Nivo, P. Nguyen, J. Yuan, S. Panda, O. Kwon, N. Edleman, T. Tjoa, J. Widodo, M. Belyansky, M. Sherony, R. Amos, H. Ng, M. Hierlemann, D. Coolbough, A. Steegen, I. Yang, J. Sudijono, T. Schiml, J. H. Ku, and C. Davis, "Stress proximity technique for performance improvement with dual stress liner at 45 nm technology and beyond," in VLSI Symp. Tech. Dig., 2006, pp. 60-61.
  • 9
    • 41149095123 scopus 로고    scopus 로고
    • M. Shima, K. Okabe, A. Yamaguchi, T. Sakoda, K. Kawamura, S. Pidin, M. Okuno, T. Owada, K. Sugimoto, J. Ogura, H. Kokura, H. Morioka, T. Watanabe, T. Isome, K. Okoshi, T. Mori, Y. Hayami, H. Minakata, A. Hatada, Y. Shimamune, A. Katakami, H. Ota, T. Sakuma, T. Miyashita, K. Hosaka, H. Fukutome, N. Tamura, T. Aoyama, K. Sukegawa, M. Nakaishi, S. Fukuyama, S. Nakai, M. Kojima, S. Sato, M. Miyajima, K. Hashimoto, and T. Sugii, High-performance low operation power transistor for 45 nm node universal applications, in VLSI Symp. Tech. Dig., 2006, pp. 156-157.
    • M. Shima, K. Okabe, A. Yamaguchi, T. Sakoda, K. Kawamura, S. Pidin, M. Okuno, T. Owada, K. Sugimoto, J. Ogura, H. Kokura, H. Morioka, T. Watanabe, T. Isome, K. Okoshi, T. Mori, Y. Hayami, H. Minakata, A. Hatada, Y. Shimamune, A. Katakami, H. Ota, T. Sakuma, T. Miyashita, K. Hosaka, H. Fukutome, N. Tamura, T. Aoyama, K. Sukegawa, M. Nakaishi, S. Fukuyama, S. Nakai, M. Kojima, S. Sato, M. Miyajima, K. Hashimoto, and T. Sugii, "High-performance low operation power transistor for 45 nm node universal applications," in VLSI Symp. Tech. Dig., 2006, pp. 156-157.
  • 10
    • 33644613512 scopus 로고    scopus 로고
    • Strained ultrahigh performance fully depleted nMOSFETs with ft of 330 GHz and sub-30-nm gate lengths
    • Mar
    • D. V. Singh, K. A. Jenkins, J. Sleight, Z. Ren, M. Ieong, and W. Haensch, "Strained ultrahigh performance fully depleted nMOSFETs with ft of 330 GHz and sub-30-nm gate lengths," IEEE Electron Device Lett., vol. 27, no. 3, pp. 191-193, Mar. 2006.
    • (2006) IEEE Electron Device Lett , vol.27 , Issue.3 , pp. 191-193
    • Singh, D.V.1    Jenkins, K.A.2    Sleight, J.3    Ren, Z.4    Ieong, M.5    Haensch, W.6
  • 12
    • 36148974380 scopus 로고    scopus 로고
    • On the low-frequency noise of pMOSFETs with embedded SiGe source/drain and fully silicided metal gate
    • Nov
    • E. Simoen, P. Verheyen, A. Shickova, R. Loo, and C. Claeys, "On the low-frequency noise of pMOSFETs with embedded SiGe source/drain and fully silicided metal gate," IEEE Electron Device Lett., vol. 28, no. 11, pp. 987-989, Nov. 2007.
    • (2007) IEEE Electron Device Lett , vol.28 , Issue.11 , pp. 987-989
    • Simoen, E.1    Verheyen, P.2    Shickova, A.3    Loo, R.4    Claeys, C.5
  • 13
    • 33646042907 scopus 로고    scopus 로고
    • Strained-silicon MOSFETs for analog applications: Utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown voltage
    • May
    • M. Kondo, N. Sugii, M. Miyamoto, Y. Hoshino, M. Hatori, W. Hirasawa, Y. Kimura, S. Kimura, Y. Kondo, and I. Yoshida, "Strained-silicon MOSFETs for analog applications: Utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown voltage," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1226-1234, May 2006.
    • (2006) IEEE Trans. Electron Devices , vol.53 , Issue.5 , pp. 1226-1234
    • Kondo, M.1    Sugii, N.2    Miyamoto, M.3    Hoshino, Y.4    Hatori, M.5    Hirasawa, W.6    Kimura, Y.7    Kimura, S.8    Kondo, Y.9    Yoshida, I.10
  • 14
    • 20444485784 scopus 로고    scopus 로고
    • Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications
    • Mar
    • N. Hakim, V. R. Rao, J. Vasi, and J. C. S. Woo, "Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications," IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 127-132, Mar. 2005.
    • (2005) IEEE Trans. Device Mater. Rel , vol.5 , Issue.1 , pp. 127-132
    • Hakim, N.1    Rao, V.R.2    Vasi, J.3    Woo, J.C.S.4
  • 15
    • 34047224487 scopus 로고    scopus 로고
    • Investigation of analogue performance for process-induced-strained PMOSFETs
    • Apr
    • J. Kuo, W. Chen, and P. Su, "Investigation of analogue performance for process-induced-strained PMOSFETs," Semicond. Sci. Technol., vol. 22, no. 4, pp. 404-407, Apr. 2007.
    • (2007) Semicond. Sci. Technol , vol.22 , Issue.4 , pp. 404-407
    • Kuo, J.1    Chen, W.2    Su, P.3
  • 16
    • 53349171726 scopus 로고    scopus 로고
    • Investigation of Coulomb mobility in nanoscale strained PMOSFETs
    • Sep
    • W. Chen, P. Su, and K. Goto, "Investigation of Coulomb mobility in nanoscale strained PMOSFETs," IEEE Trans. Nanotechnol., vol. 7, no. 5, pp. 538-543, Sep. 2008.
    • (2008) IEEE Trans. Nanotechnol , vol.7 , Issue.5 , pp. 538-543
    • Chen, W.1    Su, P.2    Goto, K.3
  • 20
    • 46149124800 scopus 로고    scopus 로고
    • The analog challenge of nanometer CMOS
    • M. Vertregt, "The analog challenge of nanometer CMOS," in IEDM Tech. Dig., 2006, pp. 1-8.
    • (2006) IEDM Tech. Dig , pp. 1-8
    • Vertregt, M.1
  • 21
    • 0020087476 scopus 로고
    • A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET
    • Feb
    • H. Lee, S. Oh, and G. Fuller, "A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET," IEEE Trans. Electron Devices, vol. ED-29, no. 2, pp. 346-348, Feb. 1982.
    • (1982) IEEE Trans. Electron Devices , vol.ED-29 , Issue.2 , pp. 346-348
    • Lee, H.1    Oh, S.2    Fuller, G.3
  • 22
    • 47349105613 scopus 로고    scopus 로고
    • Impact of process-induced strain on Coulomb scattering mobility in short-channel n-MOSFETs
    • Jul
    • W. Chen, P. Su, and K. Goto, "Impact of process-induced strain on Coulomb scattering mobility in short-channel n-MOSFETs," IEEE Electron Device Lett., vol. 29, no. 7, pp. 768-770, Jul. 2008.
    • (2008) IEEE Electron Device Lett , vol.29 , Issue.7 , pp. 768-770
    • Chen, W.1    Su, P.2    Goto, K.3
  • 24
    • 27144453403 scopus 로고    scopus 로고
    • In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs
    • Apr
    • F. Andrieu, T. Ernst, C. Ravit, M. Jurczak, G. Ghibaudo, and S. Deleonibus, "In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs," IEEE Electron Device Lett., vol. 26, no. 10, pp. 755-757, Apr. 2005.
    • (2005) IEEE Electron Device Lett , vol.26 , Issue.10 , pp. 755-757
    • Andrieu, F.1    Ernst, T.2    Ravit, C.3    Jurczak, M.4    Ghibaudo, G.5    Deleonibus, S.6
  • 25
    • 0029539658 scopus 로고
    • Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs
    • A. Mujtaba, S. Takagi, and R. Dutton, "Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs," in VLSI Symp. Tech. Dig., 1995, pp. 99-100.
    • (1995) VLSI Symp. Tech. Dig , pp. 99-100
    • Mujtaba, A.1    Takagi, S.2    Dutton, R.3
  • 28
    • 33947158623 scopus 로고    scopus 로고
    • Impact of scaling on analog performance and associated modeling needs
    • Sep
    • B. Murmann, P. Nikaeen, D. J. Connelly, and R. W. Dutton, "Impact of scaling on analog performance and associated modeling needs," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2160-2167, Sep. 2006.
    • (2006) IEEE Trans. Electron Devices , vol.53 , Issue.9 , pp. 2160-2167
    • Murmann, B.1    Nikaeen, P.2    Connelly, D.J.3    Dutton, R.W.4
  • 29
    • 0025398785 scopus 로고
    • A unified model for the Flicker noise in metal-oxide-semiconductor field-effect transistors
    • Mar
    • K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the Flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-664, Mar. 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , Issue.3 , pp. 654-664
    • Hung, K.K.1    Ko, P.K.2    Hu, C.3    Cheng, Y.C.4
  • 30
    • 0026144142 scopus 로고
    • Improved analysis of low frequency noise in field-effect MOS transistors
    • Apr
    • G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini, "Improved analysis of low frequency noise in field-effect MOS transistors," Phys. Stat. Sol. (A), vol. 124, no. 2, pp. 571-581, Apr. 1991.
    • (1991) Phys. Stat. Sol. (A) , vol.124 , Issue.2 , pp. 571-581
    • Ghibaudo, G.1    Roux, O.2    Nguyen-Duc, C.3    Balestra, F.4    Brini, J.5
  • 31
    • 0036540242 scopus 로고    scopus 로고
    • Electrical noise and RTS fluctuations in advanced CMOS devices
    • Apr./May
    • G. Ghibaudo and T. Bouchacha, "Electrical noise and RTS fluctuations in advanced CMOS devices," Microelectron. Reliab., vol. 42, no. 4/5, pp. 573-582, Apr./May 2002.
    • (2002) Microelectron. Reliab , vol.42 , Issue.4-5 , pp. 573-582
    • Ghibaudo, G.1    Bouchacha, T.2
  • 33
    • 20444492464 scopus 로고    scopus 로고
    • Device mismatch and tradeoffs in the design of analog circuits
    • Jun
    • P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, Jun. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.6 , pp. 1212-1224
    • Kinget, P.R.1
  • 34
    • 0021445655 scopus 로고
    • The design of high-performance analog circuits on digital CMOS chips
    • Jun
    • E. A. Vittoz, "The design of high-performance analog circuits on digital CMOS chips," IEEE J. Solid-State Circuits, vol. SSC-20, no. 3, pp. 657-665, Jun. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SSC-20 , Issue.3 , pp. 657-665
    • Vittoz, E.A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.