High performance sub-40 nm bulk CMOS with Dopant Confinement Layer (DCL) technique as a strain booster

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 289-292

  Ohta, H ^a   Tamura, N ^a   Fukutome, H ^a   Tajima, M ^a   Okabe, K ^a   Hatada, A ^a   Ikeda, K ^a   Ohkoshi, K ^a   Mori, T ^a   Sukegawa, K ^a   Satoh, S ^a   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONCENTRATION (PROCESS); DIELECTRIC FILMS; ELECTRON DEVICES; ELECTRON MOBILITY; GATE DIELECTRICS; GATES (TRANSISTOR); MOLECULAR BEAM EPITAXY; OPTICAL DESIGN; SPEECH TRANSMISSION; SURFACE MOUNT TECHNOLOGY;

BULK CMOS; CAPPING LAYERS; DOPANT CONCENTRATIONS; DRIVE CURRENTS; EQUIVALENT-OXIDE THICKNESS; GATE DIELECTRIC FILMS; INVERSION LAYERS; SHORT CHANNELS;

MICROSTRIP DEVICES;

EID: 50249187713     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418925     Document Type: Conference Paper

References (7)

1. T. Ghani et al.: IEDM Tech. Dig., pp. 978-980, 2003.
2. H. Ohta et al.: IEDM Tech. Dig., pp. 247-250, 2005.
3. A. Wei et al.: VLSI Tech., pp. 216-217, 2007.
4. A. Eiho et al.: VLSI Tech., pp. 218-219, 2007.
5. H. Nii et al.: IEDM Tech. Dig., pp. 685-688, 2006.
6. Z. Luo et al.: VLSI Tech., pp. 16-17, 2007.
7. T. Tyagi et al.: IEDM Tech. Dig., pp. 1070-1072, 2005.