Channel stress modulation and pattern loading effect minimization of milli-second super anneal for sub-65nm high performance SiGe CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 174-175

  Chen, Chien Hao ^a   Nieh, C F ^a   Lin, D W ^a   Ku, K C ^a   Sheu, J C ^a   Yu, M H ^a   Wang, L T ^a   Lin, H H ^a   Chang, H ^a   Lee, T L ^a   Goto, K ^a   Diaz, Carlos H ^a   Chen, S C ^a   Liang, M S ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Flash; Laser; Pattern loading; Stress; Super anneal

Indexed keywords

CHANNEL STRESS MODULATION; CURRENT DEGRADATION;

GAIN MEASUREMENT; OPTIMIZATION; POLYSILICON; RAPID THERMAL ANNEALING; SEMICONDUCTING SILICON COMPOUNDS; STRESS RELAXATION;

CMOS INTEGRATED CIRCUITS;

EID: 41149167699     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. K. Adach et al., VLSI Symp. p. 142, 2005.
2. C. H. Chen et al., VLSI Symp. p. 56, 2004.