A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 376-386

  Parashar, Angshuman ^a   Gurumurthi, Sudhanva ^a   Sivasubramaniam, Anand ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Complexity effective design; Instruction Reuse; Temporal Redundancy

Indexed keywords

COMPLEXITY-EFFECTIVE DESIGN; INSTRUCTION; REUSE; TEMPORAL REDUNDANCY;

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA REDUCTION; PROGRAM PROCESSORS;

BANDWIDTH;

EID: 4644301626     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (36)

1. A. Aggarwal and M. Franklin. Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 46-55, September 2003.
2. P. Ahuja, D. Clark, and A. Rogers. The Performance Impact of Incomplete Bypassing in Processor Pipelines. In Proceedings of the International Symposium on Microarchitecture (MICRO), November 1995.
3. A. Aletà, J. Codina, A. González, and D. Kaeli. Instruction Replication for Clustered Microarchitectures. In Proceedings of the International Symposium on Microarchitecture (MICRO), December 2003.
4. T. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 196-207, November 1999.
5. A. Baniasadi and A. Moshovos. Instruction Distribution Heuristics for Quad-Cluster Dynamically-Scheduled, Superscalar Processors. In Proceedings of the International Symposium on Computer Microarchitecture (MICRO), pages 337-347, December 2000.
6. M. Brown, J. Stark, and Y. Patt. Select-Free Instruction Scheduling Logic. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 204-213, December 2001.
7. D. Burger and T. Austin. The SimpleScalar Toolset, Version 3.0. http://www.simplescalar.com.
8. C. Constantinescu. Trends and Challenges in VLSI Circuit Reliability. IEEE Micro, 23(4): 14-19, July-August 2003.
9. Cacti 3.2. http://research.compaq.com/wrl/people/jouppi/CACTI.html.
10. R. Canal, J. Parcerisa, and A. González. Dynamic Cluster Assignment Mechanisms. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), pages 132-142, January 2002.
11. D. Citron and D. Feitelson. The Organization of Lookup Tables in Instruction Memoization. Technical Report 2000-4, Hebrew University of Jerusalem, March 2000.
12. D. Citron and D. Feitelson. Revisiting Instruction Level Reuse. In Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking (WDDD), May 2002.
13. D. Citron and D. Feitelson. "Look It Up" or "Do The Math": An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization. In Proceedings of the Workshop on Power-Aware Computer Systems, December 2003.
14. T. Ehrhart and S. Patel. Reducing the Scheduling Critical Cycle using Wakeup Prediction. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), February 2004.
15. M. Gomaa, C. Scarbrough, T. Vijaykumar, and I. Pomeranz. Transient-Fault Recovery for Chip Multiprocessors. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 98-109, June 2003.
16. HP NonStop Himalaya, http://nonstop.compaq.com/.
17. M. Hrishikesh, N. Jouppi, K. Farkas, D. Burger, S. Kackler, and P. Shivakumar. The Optimal Logic Depth Per Pipeline State is 6 to 8 FO4 Inverter Delays. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 14-24, June 2002.
18. S.-J. Lee and P.-C. Yew. On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 145-156, October 2000.
19. M. Lipasti and J. Shen. Exceeding the Dataflow Limit via Value Prediction. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 226-237, December 1996.
20. A. Mendelson and N. Suri. Designing high-performance and reliable superscalar architectures-the out of order reliable superscalar (O3RS) approach. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 473-481, June 2000.
21. S. Palacharla. Complexity-Effective Superscalar Processors. PhD thesis, University of Wisconsin - Madison, 1998.
22. S. Palacharla, N. Jouppi, and J. Smith. Complexity-Effective Superscalar Processors. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 206-218, June 1997.
23. A. Parashar, S. Gurumurthi, and A. Sivasubramaniam. A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. Technical Report CSE-04-008, The Pennsylvania State University, March 2004.
24. J. Ray, J. Hoe, and B. Falsafi. Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 214-224, December 2001.
25. S. Reinhardt and S. Mukherjee. Transient Fault Detection via Simultaneous Multithreading. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 25-36, June 2000.
26. E. Rotenberg. AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. In Proceedings of the International Symposium art Fault-Tolerant Computing (FTCS), pages 84-91, June 1999.
27. J. Shen and M. Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors (Beta Edition). McGraw Hill, 2003.
28. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), June 2002.
29. A. Sodani and G. Sohi. Dynamic Instruction Reuse. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 194-205, June 1997.
30. A. Sodani and G. Sohi. Understanding the Differences Between Value Prediction and Instruction Reuse. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 205-215, December 1998.
31. G. Sohi, M. Franklin, and K. Saluja. A Study of Time-Redundant Fault Tolerant Techniques in High Performance Pipelined Computers. In Proceedings of the International Symposium on Fault-Tolerant Computing (FTCS), pages 436-443, June 1989.
32. J. Stark, M. Brown, and Y. Patt. On Pipelining Dynamic Instruction Scheduling Logic. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 57-66, December 2000.
33. T. Vijaykumar, I. Porneranz, and K. Cheng. Transient-Fault Recovery via Simultaneous Multithreading. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 87-98. May 2002.
34. T.-Y. Yeh and Y. Patt. Alternative Implementations of Two-Level Adaptive Branch Prediction. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 124-134, May 1992.
35. J. Yi, R. Sendag, and D. Lilja. Increasing Instruction-Level Parallelism with Instruction Precomputation. In Proceedings of Euro-Par, August 2002.
36. J. Zeigler. Terrestrial Cosmic Rays. IBM Journal of Research and Development, 40(1):19-39, January 1996.