A "flight data recorder" for enabling full-system multiprocessor deterministic replay

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2003, Pages 122-133

  Xu, Min ^a   Bodik, Rastislav ^a,b,c   Hill, Mark D ^a,d  

^a University of Wisconsin Madison   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER DEBUGGING; COMPUTER SOFTWARE MAINTENANCE; MULTIPROCESSING SYSTEMS; RELIABILITY; STORAGE ALLOCATION (COMPUTER);

DETERMINISTIC REPLAY; FLIGHT DATA RECORDER;

MICROPROCESSOR CHIPS;

EID: 0038684791     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/859630.859633     Document Type: Conference Paper

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