Automating logic rectification by approximate SPFDs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 402-407

  Yang, Yu Shen ^a   Sinha, Subarna ^b   Veneris, Andreas ^a   Brayton, Robert K ^c  

^a UNIVERSITY OF TORONTO   (Canada)

^b SYNOPSYS INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; FUNCTION EVALUATION; FUZZY LOGIC; INDUSTRIAL ENGINEERING; MATHEMATICAL TRANSFORMATIONS; MECHANIZATION;

(MIN ,MAX ,+) FUNCTIONS; DESIGN AUTOMATION CONFERENCE (DAC); DESIGN ERRORS; EXPLOSION PROBLEM; NET LIST; RUNTIME PERFORMANCE; SIMULATION-BASED; SOUTH PACIFIC;

SET THEORY;

EID: 37248999358     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358019     Document Type: Conference Paper

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