Safe delay optimization for physical synthesis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 628-633

  Chang, Kai Hui ^a   Markov, Igor L ^a   Bertacco, Valeria ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED (CO); AVERAGE DELAY; CIRCUIT DELAYS; CIRCUIT TIMING; COMMERCIAL TOOLS; DELAY OPTIMIZATION; DESIGN AUTOMATION CONFERENCE (DAC); DETRIMENTAL EFFECTS; ELECTRONIC DESIGN AUTOMATION (EDA); PHYSICAL ASPECTS; PHYSICAL SYNTHESIS; RELATIVE CONTRIBUTION; RESYNTHESIS; ROUTE LENGTH; ROUTING CONGESTION; SOUTH PACIFIC;

AUTOMATION; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRONICS ENGINEERING; INDUSTRIAL ENGINEERING; MATHEMATICAL TRANSFORMATIONS; MECHANIZATION; TIMING CIRCUITS;

OPTIMIZATION;

EID: 43349102826     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358056     Document Type: Conference Paper

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