Fixing design errors with counterexamples and resynthesis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 944-949

  Chang, Kai Hui ^a   Markov, Igor L ^a   Bertacco, Valeria ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED (CO); DESIGN AUTOMATION CONFERENCE (DAC); DESIGN ERRORS; DIGITAL DESIGNS; DIGITAL SYSTEMS; ERROR MODELING; ERROR TYPES; GUIDED SEARCH; INTERNAL CIRCUITS; RESYNTHESIS; SIMULATION VECTORS; SIMULATION-BASED; SIMULATION-BASED VERIFICATION; SOUTH PACIFIC; VERIFICATION FLOWS;

CHANNEL CAPACITY; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; ERROR CORRECTION; ERRORS; FORMAL LOGIC; INDUSTRIAL ENGINEERING; MECHANIZATION; MULTIPROCESSING SYSTEMS;

ERROR ANALYSIS;

EID: 37249055506     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358111     Document Type: Conference Paper

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