Addressing the timing closure problem by integrating logic optimization and placement

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 224-231

  Gosti, W ^a   Khatri, S P ^a   Sangiovanni Vincentelli, A L ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; TIMING CIRCUITS;

TIMING CLOSURE PROBLEM;

LOGIC DESIGN;

EID: 0035212914     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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