Resynthesis of multi-level circuits under tight constraints using symbolic optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 687-693

  Kravets, Victor N ^a   Sakallah, Karem A ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN DOMAIN; FUNCTIONAL DECOMPOSITION; INDUSTRIAL CIRCUIT; MULTILEVEL CIRCUIT; SYMBOLIC DECOMPOSITION MODEL; SYMBOLIC OPTIMIZATION;

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL METHODS; FIELD PROGRAMMABLE GATE ARRAYS; ITERATIVE METHODS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION;

LOGIC DESIGN;

EID: 0036911554     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774673     Document Type: Conference Paper

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