InVerS: An incremental verification system with circuit similarity metrics and error visualization

Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Volumn , Issue , 2007, Pages 487-492

  Chang, Kai Hui ^a   Papa, David A ^a   Markov, Igor L ^a   Bertacco, Valeria ^a  

^a The Department of Civil and Environmental Engineering

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DIAGNOSIS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SYSTEM INTERCONNECTION; ERROR ANALYSIS; ERROR DETECTION; OPTIMIZATION;

DESIGN COMPLEXITY; DESIGN METHODOLOGY; VERIFICATION SYSTEM;

INTEGRATED CIRCUITS;

EID: 34548124930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.94     Document Type: Conference Paper

References (13)

1. M. S. Abadir, J. Ferguson and T. E. Kirkland, "Logic Verification via Test Generation", IEEE TCAD, pp. 138-148, Jan. 1988.
2. S. Burbeck, "Applications Programming in Smalltalk-80(TM): How to use Model-View-Controller", http://st-www.cs.uiuc.edu/users/smarch/st-docs/ mvc.html
3. C. Changfan, Y. C. Hsu and F. S. Tsai, "Timing Optimization on Routed Designs with Incremental Placement and Routing Characterization", IEEE Trans. on CAD, Feb. 2000, pp. 188-196.
4. I. Chayut, "Next-Generation Multimedia Designs: Verification Needs," DAC'06, Section 23.2, http://www.dac.com/43rd/43talkindex.html
5. N. Eén and N. Sörensson, "An Extensible SAT-solver", Theory and Applications of Satisfiability Testing, SAT, 2003, pp. 502-518.
6. J.-H. R. Jiang and R. K. Brayton, "On the Verification of Sequential Equivalence", IEEE Transactions on Computer-Aided Design, Jun. 2003, pp. 686-697.
7. D. M. Lewis, "A Hierarchical Compiled-Code Event-Driven Logic Simulator", IEEE Transactions on Computer-Aided Design, Jul. 1987, pp.601-617.
8. A. Lu, H. Eisenmann, G. Stenz and F. M. Johannes, "Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization", ICCD'98, pp. 616-621.
9. N. Shenoy and R. Rudell, "Efficient Implementation of Retiming", ICCAD'94, pp. 226-233.
10. J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske, "Simulation and Satisfiability in Logic Synthesis", IWLS 2005, pp. 161-168.
11. Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 51205. http://www-cad.eecs. berkeley.edu/~alanmi/abc/
12. http://iwls.org/iwls2005/benchmarks.html
13. http://www.si2.org/