-
1
-
-
33846645254
-
-
Berkeley Logic Synthesis and Verification Group, December Release
-
Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. December 2005 Release. http://www-cad.eecs.berkeley.edu/~alanmi/abc
-
(2005)
ABC: A System for Sequential Synthesis and Verification
-
-
-
2
-
-
0031356802
-
Disjunctive decomposition of logic functions
-
V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions," Proc. ICCAD '97, pp. 78-82.
-
(1997)
Proc. ICCAD
, pp. 78-82
-
-
Bertacco, V.1
Damiani, M.2
-
3
-
-
16244421073
-
DAG-aware circuit compression for formal verification
-
P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification", Proc. ICCAD '04, pp. 42-49.
-
Proc. ICCAD '04
, pp. 42-49
-
-
Bjesse, P.1
Boralv, A.2
-
4
-
-
0002846615
-
The decomposition and factorization of Boolean expressions
-
R. Brayton and C. McMullen, "The decomposition and factorization of Boolean expressions," Proc. ISCAS '82, pp. 29-54.
-
(1982)
Proc. ISCAS
, pp. 29-54
-
-
Brayton, R.1
McMullen, C.2
-
5
-
-
0025386807
-
Multilevel logic synthesis
-
Feb
-
R. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, "Multilevel logic synthesis", Proc. IEEE, Vol. 78, Feb.1990.
-
(1990)
Proc. IEEE
, vol.78
-
-
Brayton, R.1
Hachtel, G.2
Sangiovanni-Vincentelli, A.3
-
6
-
-
33751405387
-
Reducing structural bias in technology mapping
-
S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. ICCAD '05, pp. 519-526.
-
Proc. ICCAD '05
, pp. 519-526
-
-
Chatterjee, S.1
Mishchenko, A.2
Brayton, R.3
Wang, X.4
Kam, T.5
-
7
-
-
0028259317
-
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
-
January
-
J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE Trans. CAD, vol. 13(1), January 1994, pp. 1-12.
-
(1994)
IEEE Trans. CAD
, vol.13
, Issue.1
, pp. 1-12
-
-
Cong, J.1
Ding, Y.2
-
8
-
-
0038718554
-
Timing-driven logic bi-decomposition
-
June
-
J. Cortadella, "Timing-driven logic bi-decomposition", IEEE TCAD, vol. 22(6), June 2003, pp. 675-685.
-
(2003)
IEEE TCAD
, vol.22
, Issue.6
, pp. 675-685
-
-
Cortadella, J.1
-
9
-
-
33846644323
-
-
IWLS
-
IWLS 2005 Benchmarks, http://iwls.org/iwls2005/benchmarks.html
-
(2005)
Benchmarks
-
-
-
11
-
-
85165861144
-
SAT-based complete don't-care computation for network optimization
-
A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", DATE '05, pp. 418-423.
-
DATE '05
, pp. 418-423
-
-
Mishchenko, A.1
Brayton, R.2
-
12
-
-
85165856006
-
Scalable logic synthesis using a simple circuit structure
-
A. Mishchenko and R. Brayton, "Scalable logic synthesis using a simple circuit structure", Proc. IWLS '06. http://www.eecs.berkeley. edu/~alanmi/publications/2006/iwls06_sls.pdf.
-
Proc. IWLS '06
-
-
Mishchenko, A.1
Brayton, R.2
-
13
-
-
85165848264
-
Improvements to combinational equivalence checking
-
A. Mishchenko, S. Chatterjee, R. Brayton, and N. Eén, "Improvements to combinational equivalence checking", IWLS '06. http://www.eecs.berkeley.edu/~alanmi/publications/2006/iwls06_cec.pdf
-
IWLS '06
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
Eén, N.4
-
14
-
-
85165858745
-
Improvements to technology mapping for LUT-based FPGAs
-
A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUT-based FPGAs", FPGA '06, pp. 4149.
-
FPGA '06
, pp. 4149
-
-
Mishchenko, A.1
Chatterjee, S.2
Brayton, R.3
-
15
-
-
0003576437
-
-
John Wiley & Sons, Inc, New York, NY
-
S. Muroga, Logic design and switching theory, John Wiley & Sons, Inc., New York, NY, 1979.
-
(1979)
Logic design and switching theory
-
-
Muroga, S.1
-
17
-
-
34547175268
-
A new retiming-based technology mapping algorithm for LUT-based FPGAs
-
P. Pan and C-C. Lin, "A new retiming-based technology mapping algorithm for LUT-based FPGAs," Proc. FPGA '98, pp. 3542.
-
(1998)
Proc. FPGA
, pp. 3542
-
-
Pan, P.1
Lin, C.-C.2
-
18
-
-
0003934798
-
SIS: A system for sequential circuit synthesis
-
Technical Report, UCB/ERI, M.92/41, ERL, Dept. of EECS, UC Berkeley
-
E. Sentovich et al. "SIS: A system for sequential circuit synthesis". Technical Report, UCB/ERI, M.92/41, ERL, Dept. of EECS, UC Berkeley, 1992.
-
(1992)
-
-
Sentovich, E.1
-
19
-
-
85165845577
-
-
S. Yang. Logic synthesis and optimization benchmarks. Version 3.0. Tech. Report. Microelectronics Center of North Carolina, 1991
-
S. Yang. Logic synthesis and optimization benchmarks. Version 3.0. Tech. Report. Microelectronics Center of North Carolina, 1991.
-
-
-
|