Topologically constrained logic synthesis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 679-686

  Sinha, Subarnarekha ^a   Mishchenko, Alan ^b   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL BOOLEAN NETWORK; FUNCTIONAL DECOMPOSITION; SET OF PAIRS OF FUNCTIONS TO BE DISTINGUISHED; WIREPLANNING PROBLEM;

ALGORITHMS; BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC GATES; NUMERICAL METHODS; PROBLEM SOLVING; THEOREM PROVING;

LOGIC DESIGN;

EID: 0036917420     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774672     Document Type: Conference Paper

References (12)

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