Timing driven placement in interaction with netlist transformations

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1997, Pages 36-41

  Stenz, Guenter ^a   Riess, Bernhard M ^a   Rohfleisch, Bernhard ^a   Johannes, Frank M ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; VLSI CIRCUITS;

NETLIST TRANSFORMATIONS; PATH DELAY; STANDARD CELL CIRCUITS; TIMING DRIVEN PLACEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030679121     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/267665.267676     Document Type: Conference Paper

References (11)