A new incremental placement algorithm and its application to congestion-aware divisor extraction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 541-548

  Chatterjee, Satrajit ^a   Brayton, Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIVISOR EXTRACTION; GLOBAL ROUTERS; INCREMENTAL PLACEMENT ALGORITHM; NON-PLACEMENT-AWARE FLOW;

ALGORITHMS; COMPUTATIONAL METHODS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC WIRE; ROUTERS;

LOGIC CIRCUITS;

EID: 16244367444     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A. Caldwell, A. Kahng and I. Markov. "Can Recursive Bisection Produce Routable Placements?," In Proc. of Design Automation Conf., pages 477-482, 2000.
2. F. Corno, M. Sonza Reorda and G. Squillero. "RT-Level ITC 99 Benchmarks and First ATPG Results," IEEE Design & Test of Computers, Jul-Aug 2000.
3. H. Eisenmann and F. Johannes. "Generic Global Placement and Floorplanning," In Proc. of Design Automation Conf., pages 269-274, 1998.
4. W. Gosti et al. "Wire-planning in Logic Synthesis," In Proc. of ICCAD, pages 26-33, 1998.
5. W. Gosti, S. Khatri and A. Sangiovanni-Vincentelli. "Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement," In Proc. of ICCAD, pages 224-231, 2001.
6. P. Kudva, A. Sullivan and W. Dougherty. "Metrics for Structural Logic Synthesis," In Proc. of ICCAD, pages 551-556, 2002
7. T. Kutzschebauch and L. Stok. "Layout Driven Decomposition with Congestion Consideration," In Proc. of DATE, pages 672-676, 2002.
8. T. Kutzschebauch and L. Stok. "Congestion Aware Layout Driven Logic Synthesis," In Proc. of ICCAD, pages 216-223, 2001.
9. M. Pedram and N. Bhat. "Layout-driven Logic Restructuring and Decomposition," In Proc. of ICCAD, pages 134-137, 1991.
10. M. Pedram and N. Bhat. "Layout Driven Technology Mapping," In Proc. of Design Automation Conf., pages 99-105, 1991.
11. J. Rajski and J. Vasudevamurthy. "The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions," IEEE TRANS. on Comp. Aided Design, vol. 2, no. 6, pages 778-793, 1992.
12. E. Sentovich et al. "SIS: A System for Sequential Circuit Synthesis," Technical Report UCB/ERL M92/41, Univ. of CA at Berkeley, May 1992
13. Multi-Valued Logic Synthesis System. On the Internet: http://www-cad.eecs.berkeley.edu/Respep/Research/mvsis/