Timing optimization of FPGA placements by logic replication

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 196-201

  Beraudo, Giancarlo ^a   Lillis, John ^a  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Logic Replication; Placement; Programmable Logic; Timing Optimization

Indexed keywords

ALGORITHMS; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; OPTIMIZATION;

LOGIC REPLICATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0043136765     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775884.775885     Document Type: Conference Paper

References (12)

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