Fast and accurate rectilinear Steiner minimal tree algorithm for VLSI design

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2005, Pages 28-35

  Chu, Chris ^a   Wong, Yiu Chung ^b  

^a Iowa State University of Science and Technology   (United States)

^b Rio Design Automation   (United States)

Author keywords

Rectilinear Steiner minimal tree algorithm; Routing; Wirelength estimation

Indexed keywords

ALGORITHMS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; PARAMETER ESTIMATION; TREES (MATHEMATICS);

RECTILINEAR STEINER MINIMAL TREE ALGORITHM; ROUTING; WIRELENGTH ESTIMATION;

VLSI CIRCUITS;

EID: 29144520577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055145     Document Type: Conference Paper

References (19)

1. Chris Chu. FLUTE: Fast lookup table based wirelength estimation technique. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, pages 696-701, 2004.
2. M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, NY, 1979.
3. F. K. Hwang, On Steiner minimal trees with rectilinear distance. SIAM Journal of Applied Mathematics, 30:104-114, 1976.
4. F. K. Hwang, D. S. Richards, and P. Winter. The Steiner tree problem. Annals of Discrete Mathematics, 1992. Elsevier Science Publishers.
5. D. M. Warme, P. Winter, and M. Zachariasen. Exact algorithms for plane Steiner tree problems: A computational study. In D.Z. Du, J.M. Smith, and J.H. Rubinstein, editors, Advances in Steiner Trees, pages 81-116. Kluwer Academic Publishers, 2000.
6. GeoSteiner - software for computing Steiner trees. http://www.diku.dk/geosteiner/.
7. J. Griffith, G. Robins, J. S. Salowe, and T. Zhang. Closing the gap: Near-optimal Steiner trees in polynomial time. IEEE Trans. Computer-Aided Design, 13(11):1351-1365, November 1994.
8. I. I. Mandoiu, V. V. Vazirani, and J. L. Ganley. A new heuristic for rectilinear Steiner trees. In Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, 1999.
9. M. Borah, R. M. Owens, and M. J. Irwin. An edge-based heuristic for Steiner routing. 13(12): 1563-1568, December 1994.
10. Hai Zhou. Efficient Steiner tree construction based on spanning graphs. In Proc. Intl. Symp. on Physical Design, pages 152-157, 2003.
11. H. Zhou, N. Shenoy, and W. Nicholls. Efficient spanning tree construction with delaney triangulation. Information Processing Letters, 81(5), 2002.
12. J. Soukup. Circuit layout. Proceedings of IEEE, 69:1281-1304, October 1981.
13. H. Chen, C. Qiao, F. Zhou, and C.-K. Cheng. Refined single trunk tree: A rectilinear Steiner tree generator for interconnect prediction. In Proc. ACM Intl. Workshop on System Level Interconnect Prediction, pages 85-89, 2002.
14. C. J. Alpert. The ISPD98 Circuit Benchmark Suite. In Proc. Intl. Symp. on Physical Design, pages 80-85, 1998. http://vlsicad.cs.ucla.edu/~cheese/ispd98.html.
15. Andrew B. Kahng and Ion Mandoiu. RMST-Pack: Rectilinear minimum spanning tree algorithms, http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/RSMT/RMST/.
16. M. Hanan. On Steiner's problem with rectilinear distance. SIAM Journal of Applied Mathematics, 14:255-265, 1966.
17. Chris Chu. FLUTE: Fast lookup table based technique for RSMT construction and wirelength estimation, http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/RSMT/.
18. A. E. Caldwell, A. B. Kahng, and I. L. Markov. VLSI CAD Bookshelf. http://www.gigascale. org/bookshelf/.
19. Natarajan Viswanathan and Chris Chu. FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In Proc. Intl. Symp. on Physical Design, pages 26-33, 2004.