Parallelizing CAD: A timely research agenda for EDA

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 12-17

  Catanzaro, Bryan ^a   Keutzer, Kurt ^a   Su, Bor Yiing ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Framework; Manycore; Parallelization; Pattern

Indexed keywords

CAD APPLICATIONS; FRAMEWORK; MANYCORE; PARALLELIZATION; PATTERN;

APPLICATIONS; DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING;

COMPUTER AIDED DESIGN;

EID: 51549109604     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555773     Document Type: Conference Paper

References (55)

1. C. Alexander et al. A Pattern Language: Towns, Buildings, Construction. Oxford University Press, USA, 1977.
2. K. Asanovic et al. The landscape of parallel computing research: a view from Berkeley. Technical report, Electrical Engineering and Computer Sciences, University of California at Berkeley, 2006.
3. K. Asanovic et al. The landscape of parallel computing research: a view from Berkeley 2.0. Technical report, Electrical Engineering and Computer Sciences, University of California at Berkeley, 2007.
4. Z. Cao et al. Dprouter: A fast and accurate dynamic-patternbased global routing algorithm. ASPDAC '07:, pp. 256-261, 2007.
5. T. F. Chan et al. MPL6: a robust multilevel mixed-size placement engine. ISPD '05, pp. 227-229, 2005.
6. T.-C. Chen, Y.-W. Chang, and S.-C. Lin. Imf: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD '05, pp. 159-164, 2005.
7. T.-C. Chen et al. A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD '06, pp. 187-192, 2006.
8. M. Cho et al. Boxrouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD '07, pp. 503-508, 2007.
9. C. Chu and Y.-C. Wong. Fast and accurate rectilinear steiner minimal tree algorithm for vlsi design. ISPD '05: pp. 28-35, 2005.
10. E. Gamma et al. Design Patterns: Elements of Reusable Object-Oriented Software. Addison-Wesley Professional, USA, 1994.
11. D. Garlan and M. Shaw. An introduction to software architecture. Technical report, Pittsburgh, PA, USA, 1994.
12. A. B. Kahng and Q. Wang. A faster implementation of aplace. ISPD '06, pp. 218-220, New York, NY, USA, 2006.
13. M. Kleinhans et al. VLSI placement by quadratic programming and slicing optimization. IEEE Trans. on CAD, 10(3):356-365, 1991.
14. J.-M. Lin and Y.-W. Chang. Tcg-s: orthogonal coupling of p*-admissible representations for general floorplans. DAC '02, pp. 842-847, 2002.
15. S. MacDonald et al. From patterns to frameworks to parallel programs. Parallel Computation, 28(12):1663-1683, 2002.
16. T. G. Mattson, B. A. Sanders, and B. L. Massingill. Patterns for Parallel Programming. Addison-Wesley Professional, USA, 2004.
17. A. N. Ng et al. Solving hard instances of floorplacement. ISPD'06: pp. 170-177, 2006.
18. M. Pan and C. Chu. Fastroute 2.0: A high-quality and efficient global router. Asia South Pacific-DAC '07: pp. 250-255, 2007.
19. P. Spindler and F. M. Johannes. Fast and robust quadratic placement combined with an exact linear net model. In ICCAD'06: pp. 179-186, 2006.
20. T. Taghavi, et al. Dragon2006: blockage-aware congestion- controlling mixed-size placer. ISPD '06, pp. 209-211, 2006.
21. N. Viswanathan et al. Rql: global placement via relaxed quadratic spreading and linearization. DAC '07, pp. 453-458, 2007.
22. N. Viswanathan, M. Pan, and C. Chu. Fastplace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. Asia South Pacific-DAC '07, pp. 135-140, 2007.
23. H. Murata et al. VLSI Module Placement Based on Rectangle-Packing by the Sequence Pair, IEEE Trans. on CAD 15(12), pp. 1518-1524, 1996.
24. J. Cong, J. Fang, and K. Khoo. DUNE: a multi-layer gridless routing system with wire planning. ISPD'00, pp. 12-18, 2000.
25. E. Carlson, R. Rutenbar. A Scanline Data Structure Processor for VLSI Geometry Checking, IEEE Trans. on CAD 6(5), pp. 780-794, September 1987
26. J. Mitra, P. Yu, D. Pan. RADAR: RET-aware detailed routing using fast lithography simulations, DAC'05, pp. 369-372, 2005.
27. C. Chiang et al. Fast and efficient phase conflict detection and correction in standard-cell layouts. ICCAD'05, pp. 149-156, 2005.
28. N. Saluja and S. Khatri. A robust algorithm for approximate compatible observability don't care (CODC) computation. DAC'04, pp 7-11, 2004.
29. C. Leiserson and J. Saxe. Retiming Synchronous Circuitry, Algorithmica, vol. 6, pp. 5-35, 1991.
30. K. Keutzer. DAGON: technology binding and local optimization by DAG matching. DAC'87, pp. 341-347, 1987.
31. E. Lehman et al. Logic decomposition during technology mapping, IEEE Trans. on CAD 16(8):813-834, 1997.
32. A. Ramalingam et al. An accurate sparse matrix based framework for statistical static timing analysis. DAC'06, pp. 231-236, 2006.
33. S. Devadas, et al. Computation of floating mode delay in combinational circuits: practice and implementation, IEEE Trans. on CAD 12(12):1924-1936, 1993.
34. N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli. Graph algorithms for clock schedule optimization. ICCAD'92, pp. 132-136, 1992.
35. P. Goel and B. Rosales, PODEM-X: An automatic test generation system for VLSI logic structures. DAC'81, 1981.
36. H. Fujiwara. FAN: A Fanout-Oriented Test Pattern Generation Algorithm, Proc. Int'l Symp. Circuits and Systems, pp. 671-674, 1985.
37. S.-T. Cheng, R. Brayton. Synthesizing multi-phase HDL programs, Verilog HDL Conference, pp. 67-76, 1996.
38. S. Devadas, K. Keutzer, S. Malik, Delay computation in combinational logic circuits: theory and algorithms, ICCAD'91, pp. 176-179, 1991.
39. E. Goldberg, M. Prasad, and R. Brayton. Using SAT for combinational equivalence checking. DATE'01, pp. 114-121, 2001.
40. S. Malik et al. Logic Verification Using Binary-Decision Diagrams in a Logic Synthesis Environment. ICCAD'88, pp. 6-9, 1988.
41. A. Cimatti, et al. NuSMV 2: An OpenSource Tool for Symbolic Model Checking, CAV'02, pp. 359-364, 2002.
42. A. Kolbi, J. Kukula, R. Damiano, Symbolic RTL simulation, DAC'01, pp. 47-52, 2001.
43. L. Nagel. SPICE2: A Computer Program to Simulate Semiconductor Circuits, Memorandum No. ERL-M520, University of California, Berkeley, May 1975.
44. S. Srivastava and J. Roychowdhury. Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations, DAC'07, pp. 136-141, 2007.
45. A. Mishchenko, S. Chatterjee and R. Brayton, DAG-aware AIG rewriting: a fresh look at combinatorial logic synthesis, DAC'06, pp. 532-535, 2006.
46. R. Brayton et al. Logic Minimization Algorithms for VLSI Synthesis, Kluwer, Boston, 1984.
47. T.-C. Chen and Y.-W. Chang. Modern floorplanning based on fast simulated annealing, ISPD'05, pp. 104-112, 2005.
48. C. Fiduccia, R. Mattheyses. A Linear-Time Heuristic for Improving Network Partitions, DAC'82, pp. 175-181, 1982.
49. M. Hsueh. Symbolic layout and compaction, PhD Thesis, University of California, Berkeley, 1980.
50. T. Larrabee. Test pattern generation using Boolean satisfiability, IEEE TCAD, 11, 1, pp. 4-15, 1992.
51. V. Krishnaswamy, P. Banerjee. Actor Based Parallel VHDL Simulation Using Time Warp, Parallel and Distributed Simulation 1996, pp. 135-142.
52. A. Stam. A Framework for Coordinating Parallel Branch and Bound Algorithms, LNCS Coordination Models and Languages, pp. 523-532, 2002.
53. W.-M. Hwu et al. Implicitly parallel programming models for thousand-core microprocessors, DAC'07, pp. 754-75.
54. Anderson, E., et al., 1999 LAPACK Users' Guide (Third Ed.). Society for Industrial and Applied Mathematics.
55. Lumsdaine, A., et al., Challenges in Parallel Graph Processing. Parallel Processing Letters, 17(1):5-20, 2007.