TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 842-847

  Lin, Jai Ming ^a   Chang, Yao Wen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

WIRELENGTH OPTIMIZATION;

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER AIDED ENGINEERING; CONSTRAINT THEORY; CONVERGENCE OF NUMERICAL METHODS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PERTURBATION TECHNIQUES;

VLSI CIRCUITS;

EID: 0036051250     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. B*-trees: A new representation for non-slicing floorplans
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3. Corner block list: An effective and efficient topological representation of non-slicing floorplan
4. Optimization by simulated annealing
5. Module placement with boundary constraints using the sequence-pair
6. TCG: A transitive closure graph-based representation for non-slicing floorplans
7. VLSI floorplanning with boundary constraints based on corner block list
8. Rectangle-packing based module placement
9. VLSI/PCB placement with obstacles based on sequence pair
10. Module placement on BSG-Structure and IC layout applications
11. Automatic floorplan design
12. An enhanced perturbing algorithm for floorplan design using the O-tree representation
13. The quarter-state sequence (Q-sequence) to represent teh floorplan and applications to layout optimization
14. FAST-SP: A fast alorithm for block placement based on sequence pair
15. A new algorithm for floorplan design