Logic verification using binary decision diagrams in a logic synthesis environment

Volumn , Issue , 1988, Pages 6-9

  Malik, Sharad ^a   Wang, Albert R ^a   Brayton, Robert K ^a   Sangiovanni Vincentelli, Alberto ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION THEORY AND ANALYSIS; LOGIC CIRCUITS, COMBINATORIAL;

BINARY DECISION DIAGRAMS; FORMAL VERIFICATION; FUNCTIONAL EQUIVALENCE; LOGIC VERIFICATION; MULTILEVEL LOGIC SYNTHESIS;

COMPUTER METATHEORY;

EID: 0024172602     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)