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Volumn , Issue , 2007, Pages 503-508

BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router

Author keywords

[No Author keywords available]

Indexed keywords

3-D MAPPING; COMPUTER-AIDED DESIGN; GLOBAL ROUTING; INTEGER LINEAR PROGRAMMING; INTERNATIONAL CONFERENCES; ITS ARCHITECTURE; LAYER ASSIGNMENT; MULTI-LAYER ROUTING; ROUTABILITY; ROUTING STABILITY; VLSI DESIGNS; WIRE LENGTHS;

EID: 43349093583     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397314     Document Type: Conference Paper
Times cited : (107)

References (35)
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  • 2
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  • 5
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    • Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment
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    • D. Wu, J. Hu, and R. Mahapatra, "Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment," in Proc. Int. Symp. on Physical Design. Apr 2005.
    • (2005) Proc. Int. Symp. on Physical Design
    • Wu, D.1    Hu, J.2    Mahapatra, R.3
  • 6
    • 0035513318 scopus 로고    scopus 로고
    • A Survey On Multi-net Global Routing for Integrated Circuits
    • J. Hu and S. Sapatnekar, "A Survey On Multi-net Global Routing for Integrated Circuits." Integration, the VLSI Journal, vol. 31, no. 1, pp. 1-49, 2002.
    • (2002) Integration, the VLSI Journal , vol.31 , Issue.1 , pp. 1-49
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  • 16
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    • FastRoute: A Step to Integrate Global Routing into Placement
    • Nov
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    • (2006) Proc. Int. Conf. on Computer Aided Design
    • Pan, M.1    Chu, C.2
  • 19
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    • Wire packing: A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution
    • R. Kay and R. A. Rutenbar, "Wire packing: A strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution," in Proc. Int. Symp. on Physical Design, 2000.
    • (2000) Proc. Int. Symp. on Physical Design
    • Kay, R.1    Rutenbar, R.A.2
  • 25
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  • 28
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    • PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs
    • Feb
    • L. McMurchie and C. Ebeling, "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs." in ACM Symposium on FPGAs. Feb 1995.
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  • 33
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    • FLUTE: Fast Lookup Table Based Wirelength Estimation Technique
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    • C. C. N. Chu, "FLUTE: Fast Lookup Table Based Wirelength Estimation Technique." in Proc. Int. Conf. on Computer Aided Design, Nov 2004.
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  • 34
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.