Symbolic RTL simulation

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 47-52

  Kölbl, Alfred ^a   Kukula, James ^b   Damino, Robert ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ERROR ANALYSIS; LARGE SCALE SYSTEMS; LOGIC GATES; SEMANTICS; SHIFT REGISTERS; SWITCHING;

SYMBOLIC SIMULATION;

INTEGRATED CIRCUIT TESTING;

EID: 0034848147     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156106     Document Type: Article

References (11)

1. Formally verifying a microprocessor using a simulation methodology
2. Formal verification of VHDL using VHDL-like ACL2 models
3. Symbolic simulation and verification of VHDL with ACL2
4. Formal hardware verification by symbolic ternary trajectory evaluation
5. Graph-based algorithms for Boolean function manipulation
6. Computing binary decision diagrams for VHDL data types
7. Symbolic timing simulation using cluster scheduling
8. Generation of BDDs from hardware algorithm descriptions
9. Formal verification by symbolic evaluation of partially-ordered trajectories
10. Reliable verification using symbolic simulation with scalar values