-
1
-
-
3042573007
-
-
Amba Bus, Arm, http://www.arm.com
-
-
-
-
2
-
-
0036149420
-
Networks on chips: "A new SoC paradigm"
-
Benini, L., and De Micheli, G. Networks on Chips: "A new SoC paradigm", IEEE Computer, vol. 35 (1), 2002, pp. 70-781.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-781
-
-
Benini, L.1
De Micheli, G.2
-
4
-
-
84893751424
-
Transaction-level models for amba bus architecture using systemC 2.0
-
Munich, Germany
-
Caldari, M., Conti, M., Pieralisi, L., Turchetti, C., Coppola, M., and Curaba, S., "Transaction-level models for Amba bus architecture using SystemC 2.0". Proc. Design Automation Conf., Munich, Germany, 2003, pp. 20026-20031.
-
(2003)
Proc. Design Automation Conf.
, pp. 20026-20031
-
-
Caldari, M.1
Conti, M.2
Pieralisi, L.3
Turchetti, C.4
Coppola, M.5
Curaba, S.6
-
5
-
-
0033899694
-
Behaviour modeling of micro-electro-mechanical systems (MEMS) with statistical performance variability reduction and sensitivity analysis
-
Dewey, A., Ren, H., Zhang, T. "Behaviour modeling of micro-electro-mechanical systems (MEMS) with statistical performance variability reduction and sensitivity analysis". IEEE Trans. Circuits and Systems, 47 (2), 2002, pp. 105-113.
-
(2002)
IEEE Trans. Circuits and Systems
, vol.47
, Issue.2
, pp. 105-113
-
-
Dewey, A.1
Ren, H.2
Zhang, T.3
-
6
-
-
84875818136
-
-
Cierto virtual component co-design (VCC), Cadence Design Systems, see http://www.cadence.com/articles/vcc.html
-
Cadence Design Systems
-
-
-
7
-
-
3042628797
-
IPSIM: SystemC 3.0 enhancements for refinement
-
Coppola, M., Curaba, S., Grammatikakis M.D. and Maruccia, G. "IPSIM: SystemC 3.0 enhancements for refinement", Proc. Design Automation & Test in Europe Conf., 2003, pp 20106-111.
-
(2003)
Proc. Design Automation & Test in Europe Conf.
, pp. 20106-20111
-
-
Coppola, M.1
Curaba, S.2
Grammatikakis, M.D.3
Maruccia, G.4
-
8
-
-
1242321464
-
-
Coppola, M., Curaba, S., Grammatikakis, M., Maruccia, G., and Papariello, F. "The OCCN user manual". Available from http://occn.sourceforge.net
-
The OCCN User Manual
-
-
Coppola, M.1
Curaba, S.2
Grammatikakis, M.3
Maruccia, G.4
Papariello, F.5
-
9
-
-
0036760609
-
A scalable high-performance computing solution for networks on chips
-
Forsell, M. "A scalable high-performance computing solution for networks on chips", IEEE Micro, 22 (5), pp. 46-55, 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.5
, pp. 46-55
-
-
Forsell, M.1
-
10
-
-
84893687806
-
A generic architecture for on-chip packet-switched interconnections
-
Guerrier, P., and Greiner, A. "A generic architecture for on-chip packet-switched interconnections", Proc. Design, Automation & Test in Europe Conf., 2000, pp. 250-256.
-
(2000)
Proc. Design, Automation & Test in Europe Conf.
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
12
-
-
84893765281
-
Design space exploration for optimizing on-chip communication networks
-
Lahiri, K., Raghunathan, A., and Dey, S. "Design space exploration for optimizing on-chip communication networks", to appear, IEEE Trans. CAD Integr. Circuits and Systems.
-
IEEE Trans. CAD Integr. Circuits and Systems
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
-
13
-
-
0035368837
-
System level performance analysis for designing on-chip communication architectures
-
Lahiri, K., Raghunathan, A., and Dey, S. "System level performance analysis for designing on-chip communication architectures", IEEE Trans. CAD Integr. Circuits and Systems, 20 (6), 2001, pp.768-783.
-
(2001)
IEEE Trans. CAD Integr. Circuits and Systems
, vol.20
, Issue.6
, pp. 768-783
-
-
Lahiri, K.1
Raghunathan, A.2
Dey, S.3
-
14
-
-
0042111484
-
-
Kluwer Academic Publisher, ISBN: 1-4020-7392-5
-
Networks on Chip, Eds. Jantsch, A. and Tenhunen, H. Kluwer Academic Publisher, 2003, ISBN: 1-4020-7392-5.
-
(2003)
Networks on Chip
-
-
Jantsch, A.1
Tenhunen, H.2
-
15
-
-
0036857007
-
StepNP: A system-level exploration platform for network processors
-
Paulin, P., Pilkington, C., and Bensoudane E., "StepNP: A system-level exploration platform for network processors", IEEE Design and Test, 2002, 19(6), 17-26
-
(2002)
IEEE Design and Test
, vol.19
, Issue.6
, pp. 17-26
-
-
Paulin, P.1
Pilkington, C.2
Bensoudane, E.3
-
16
-
-
3042580158
-
-
Raw
-
Raw. Available from http://www.cag.lcs.mit.edu/raw
-
-
-
-
17
-
-
3042631319
-
STBus communication system: Concepts and definitions
-
Scandurra A., Falconeri, G., Jego, B., "STBus communication system: concepts and definitions", internal document, STM, 2002.
-
(2002)
Internal Document, STM
-
-
Scandurra, A.1
Falconeri, G.2
Jego, B.3
-
18
-
-
3042628798
-
STBus communication system: Architecture specification
-
Scandurra A., "STBus communication system: architecture specification", internal document, STM, 2002.
-
(2002)
Internal Document, STM
-
-
Scandurra, A.1
-
19
-
-
3042570578
-
-
VSI Alliance
-
VSI Alliance, http://www.vsi.org/
-
-
-
-
20
-
-
84948968522
-
Design space exploration of streaming multiprocessor architectures
-
San Diego, Ca
-
Zivkovic, V.D., van der Wolf, P., Deprettere, E.F. et al. "Design space exploration of streaming multiprocessor architectures", IEEE Workshop Sign. Proc. Syst., San Diego, Ca, 2002.
-
(2002)
IEEE Workshop Sign. Proc. Syst.
-
-
Zivkovic, V.D.1
Van der Wolf, P.2
Deprettere, E.F.3
-
21
-
-
0037029761
-
Integrated hierarchical design of micro-electro-fluidic systems using SystemC
-
Zhang, T., Chakrabarty, K., Fair, R.B. "Integrated hierarchical design of micro-electro-fluidic systems using SystemC". Microelectronics J., 33, 2002, pp. 459-470.
-
(2002)
Microelectronics J.
, vol.33
, pp. 459-470
-
-
Zhang, T.1
Chakrabarty, K.2
Fair, R.B.3
|