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Volumn , Issue , 2004, Pages 174-179

OCCN: A network-on-chip modeling and simulation framework

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED HARDWARE; ON-CHIP BUSES; ON-CHIP COMMUNICATION ARCHITECTURES (OCCA); PROTOCOL REFINEMENT;

EID: 3042660211     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269226     Document Type: Conference Paper
Times cited : (23)

References (21)
  • 1
    • 3042573007 scopus 로고    scopus 로고
    • Amba Bus, Arm, http://www.arm.com
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: "A new SoC paradigm"
    • Benini, L., and De Micheli, G. Networks on Chips: "A new SoC paradigm", IEEE Computer, vol. 35 (1), 2002, pp. 70-781.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-781
    • Benini, L.1    De Micheli, G.2
  • 5
    • 0033899694 scopus 로고    scopus 로고
    • Behaviour modeling of micro-electro-mechanical systems (MEMS) with statistical performance variability reduction and sensitivity analysis
    • Dewey, A., Ren, H., Zhang, T. "Behaviour modeling of micro-electro-mechanical systems (MEMS) with statistical performance variability reduction and sensitivity analysis". IEEE Trans. Circuits and Systems, 47 (2), 2002, pp. 105-113.
    • (2002) IEEE Trans. Circuits and Systems , vol.47 , Issue.2 , pp. 105-113
    • Dewey, A.1    Ren, H.2    Zhang, T.3
  • 6
    • 84875818136 scopus 로고    scopus 로고
    • Cierto virtual component co-design (VCC), Cadence Design Systems, see http://www.cadence.com/articles/vcc.html
    • Cadence Design Systems
  • 9
    • 0036760609 scopus 로고    scopus 로고
    • A scalable high-performance computing solution for networks on chips
    • Forsell, M. "A scalable high-performance computing solution for networks on chips", IEEE Micro, 22 (5), pp. 46-55, 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 46-55
    • Forsell, M.1
  • 13
    • 0035368837 scopus 로고    scopus 로고
    • System level performance analysis for designing on-chip communication architectures
    • Lahiri, K., Raghunathan, A., and Dey, S. "System level performance analysis for designing on-chip communication architectures", IEEE Trans. CAD Integr. Circuits and Systems, 20 (6), 2001, pp.768-783.
    • (2001) IEEE Trans. CAD Integr. Circuits and Systems , vol.20 , Issue.6 , pp. 768-783
    • Lahiri, K.1    Raghunathan, A.2    Dey, S.3
  • 14
    • 0042111484 scopus 로고    scopus 로고
    • Kluwer Academic Publisher, ISBN: 1-4020-7392-5
    • Networks on Chip, Eds. Jantsch, A. and Tenhunen, H. Kluwer Academic Publisher, 2003, ISBN: 1-4020-7392-5.
    • (2003) Networks on Chip
    • Jantsch, A.1    Tenhunen, H.2
  • 15
    • 0036857007 scopus 로고    scopus 로고
    • StepNP: A system-level exploration platform for network processors
    • Paulin, P., Pilkington, C., and Bensoudane E., "StepNP: A system-level exploration platform for network processors", IEEE Design and Test, 2002, 19(6), 17-26
    • (2002) IEEE Design and Test , vol.19 , Issue.6 , pp. 17-26
    • Paulin, P.1    Pilkington, C.2    Bensoudane, E.3
  • 16
    • 3042580158 scopus 로고    scopus 로고
    • Raw
    • Raw. Available from http://www.cag.lcs.mit.edu/raw
  • 18
    • 3042628798 scopus 로고    scopus 로고
    • STBus communication system: Architecture specification
    • Scandurra A., "STBus communication system: architecture specification", internal document, STM, 2002.
    • (2002) Internal Document, STM
    • Scandurra, A.1
  • 19
    • 3042570578 scopus 로고    scopus 로고
    • VSI Alliance
    • VSI Alliance, http://www.vsi.org/
  • 21
    • 0037029761 scopus 로고    scopus 로고
    • Integrated hierarchical design of micro-electro-fluidic systems using SystemC
    • Zhang, T., Chakrabarty, K., Fair, R.B. "Integrated hierarchical design of micro-electro-fluidic systems using SystemC". Microelectronics J., 33, 2002, pp. 459-470.
    • (2002) Microelectronics J. , vol.33 , pp. 459-470
    • Zhang, T.1    Chakrabarty, K.2    Fair, R.B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.