Security Wrappers and Power Analysis for SoC Technologies

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2003, Pages 162-167

  Gebotys, C H ^a   Zhang, Y ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Adiabatic; Design; Performance; Security; VLIW

Indexed keywords

ADIABATIC TECHNOLOGY; NANOMETER TECHNOLOGY; SECURITY; SECURITY WRAPPERS; VLIW;

ALGORITHMS; COST EFFECTIVENESS; CRYPTOGRAPHY; ENERGY DISSIPATION; MOBILE COMPUTING; NETWORK PROTOCOLS; QUALITY OF SERVICE; SECURITY SYSTEMS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 1142275613     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CODESS.2003.1275277     Document Type: Conference Paper

References (11)

1. P.Kocher, "Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems", LNCS, 1998.
2. L.Benini, G.DeMicheli, "Networks on Chips: A New SOC Paradigm" Computer, Vol.35, No.1, Jan 2002, pp.70-78
3. P.Liardet, N.Smart "Preventing SPA/DPA in ECC systems using the Jacobi Form", LNCS 2162, May 2001, pp391-401
4. "Star*Core 140 DSP Core Reference Manual", Motorola/Lucent, Sept 1999.
5. S.Ravi, A.Raghunathan, N.Potlapally "Securing Wireless Data: System architecture challenges", ISSS, 2002, pp. 195-200.
6. P.Kocher, J.Jaffe, B.Jun "Differential Power Analysis" Crypto'99, LNCS 1666, 1999
7. T.Messerges, E.Dabbish, R.Sloan "Investigations of Power analysis attacks on Smartcards" USENIX workshop on Smartcard Technology, 1999.
8. M.Dalpasso, A.Bogliolo, L.Benini "Hardware /Software IP Protection", Proceedings of DAC, 2000.
9. C.Yeh, J.Lou and J.Kuo, "1.5 V CMOS full-swingenergy efficient logic (EEL) circuit suitable for low-voltage andlow-power VLSI", Electronics Letters, 33(16), 1997, pp. 1375-1376
10. Y.Zhang, H.Chen, J.Kuo, "0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI", Electronics Letters, 38(24), 2002, pp. 1497-1499
11. C.Gebotys, R.Gebotys, "Secure Elliptic Curve Implementations: An analysis of resistance to power-attacks in a DSP processor", CHES 2002, LNCS 2523, pp 114-128.