Leakage minimization of SRAM cells in a dual-14 and dual-TOX technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 7, 2008, Pages 851-860

  Amelifard, Behnam ^b   Fallah, Farzan ^a,c   Pedram, Massoud ^a,b  

^a IEEE

^b University of Southern California   (United States)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Low power design; Multiple Tox; Multiple Vt; Static random access memory (SRAM); Subthreshold leakage; Tunneling gate leakage

Indexed keywords

ARSENIC COMPOUNDS; MOSFET DEVICES; VLSI CIRCUITS;

CMOS SCALING; DEEP SUBMICROMETER (DSM); GATE-LEAKAGE CURRENTS; LEAKAGE MINIMIZATION; LOW THRESHOLD VOLTAGE; OXIDE THICKNESSES; SRAM CELLS; SUB THRESHOLDS;

LEAKAGE CURRENTS;

EID: 48149106520     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2000459     Document Type: Article

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