Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Amelifard, Behnam ^a   Fallah, Farzan ^b   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODERS; LEAKAGE POWER DISSIPATION; SENSE AMPLIFIERS; SRAM DESIGN FLOW;

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 34047187529     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. Y. Taur, "CMOS scaling and issues in sub-0.25 μm systems," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE, 2001, pp. 27-45.
2. C. Molina, C. Aliagas, M. Garcia, A. Gonzalez, and J. Tubella, "Non redundant data cache," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 274-277.
3. N. Sirisantana, L. Wei, and K. Roy, "High performance low power CMOS circuits using multiple channel length and multiple oxide thickness," in Proc. Int. Conf. on Computer Design, 2000, pp. 227-232.
4. M. Togo, K. Noda, and T. Tanigawa, "Multiple-thickness gate oxide and dual-gate technologies for high-performance logic embedded DRAMs," in IEDM Tech. Dig., 1998, pp. 347-350.
5. K. Zhang et al., "SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction," IEEE J. Solid-State Circuits, vol. 40, no. 4, Apr. 2005, pp. 895-901.
6. C. Kim and K. Roy, "Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessor," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2002, pp. 251-254.
7. A. Agarwal and K. Roy, "A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 18-21.
8. N. Azizi, F. Najm, and A. Moshovos, "Low-leakage asymmetric-cell SRAM," IEEE Trans. on Very Large Scale Integration Systems, vol. 11, no. 4, Aug. 2003, pp. 701-715.
9. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations," IEEE Trans. on Very Large Scale Integration Systems, vol. 13, no. 3, Mar. 2005, pp. 349-357.
10. R. Preston, "Register files and caches," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE, 2001, pp. 285-308.
11. H. Qin, Y. Cao, D. Markovic, A, Vladimirescu, and J. Rabaey, "SRAM leakage suppression by minimizing standby supply voltage," in Proc. Int. Symposium on Quality Electronic Design, Mar. 2004.
12. V. De et al., "Techniques for leakage power reduction," in Design of High-Performance Microprocessor Circuit, Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ:IEEE, 2001, pp. 285-308.
13. rd level cache on an Itanium microprocessor," in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2002, pp. 112-113.
14. A. Agarwal, C. Kim, S. Mukhopadhyay, and K. Roy, "Leakage in nano-scale technologies: mechanisms, impact and design considerations," in Proc. of Design Automation Conf., 2004, pp. 6-11.
15. D. Lee, D. Blaauw, and D. Sylvester, "Gate oxide leakage current analysis and reduction for VLSI circuits," IEEE Trans. on Very Large Scale Integration Systems, vol. 12, no. 2, Feb. 2004, pp. 155-166.
16. F. Hamzaoglu and M. Stan, "Circuit-level techniques to control gate leakage for sub-100nm CMOS," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2002, pp. 60-63.
17. A. Sirvastava, "Simultaneous Vt selection and assignment for leakage optimization," in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 146-151.
18. http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
19. A. J. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 658-665.
20. A. Sultania, D. Sylvester, and S. Sapatnekar, "Tradeoffs between gate oxide leakage and delay for dual Tox circuits," in Proc. Design Automation Conf., 2004, pp. 761-766.
21. http://synopsys.com/products/mixedsignal/hspice/hspice.html