Characterization and modeling of run-time techniques for leakage power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 11, 2004, Pages 1221-1232

  Tsai, Yuh Fang ^a   Duarte, David E ^b   Vijaykrishnan, N ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Data preserving; Leakage power; Low power; Power estimation; Run time leakage reduction; Technology scaling; Very large scale integration (VLSI) circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT REGULATORS; GATES (TRANSISTOR); POWER SUPPLY CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; STANDBY POWER SYSTEMS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; VLSI CIRCUITS;

DATA PRESERVING; LEAKAGE POWER; POWER ESTIMATION; RUN-TIME LEAKAGE REDUCTION; TECHNOLOGY SCALING;

LEAKAGE CURRENTS;

EID: 9244264947     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.836315     Document Type: Article

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