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Volumn , Issue , 2000, Pages 27-45

CMOS scaling and issues in sub-0.25 μm systems

Author keywords

CMOS integrated circuits; Insulators; Logic gates; MOSFET circuits; Silicon; Threshold voltage; Voltage control

Indexed keywords

ELECTRIC INSULATORS; LOGIC GATES; SILICON; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

EID: 84876551598     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470544365.ch2     Document Type: Chapter
Times cited : (14)

References (15)
  • 3
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    • Small-Geometry MOS Transistors: Physics and Modeling of Surface- and Buried-Channel MOSFETs
    • Stanford University
    • T. N. Nguyen, “Small-Geometry MOS Transistors: Physics and Modeling of Surface- and Buried-Channel MOSFETs,” Ph.D. Thesis, Stanford University, 1984.
    • (1984) Ph.D. Thesis
    • Nguyen, T.N.1
  • 4
    • 0032187666 scopus 로고    scopus 로고
    • Generalized Scale Length for Two-Dimensional Effects in MOSFETs,”
    • D. J. Frank, Y. Taur, and H. -S. Wong, “Generalized Scale Length for Two-Dimensional Effects in MOSFET’s,” IEEE Electron Device Lett., vol. 19, p. 385 (1998).
    • (1998) IEEE Electron Device Lett , vol.19 , pp. 385
    • Frank, D.J.1    Taur, Y.2    Wong, H.-S.3
  • 5
    • 0031122158 scopus 로고    scopus 로고
    • CMOS Scaling into the Nanometer Regime
    • Y. Taur et al., “CMOS Scaling into the Nanometer Regime,” IEEE Proceedings, p. 486 (1997).
    • (1997) IEEE Proceedings , pp. 486
    • Taur, Y.1
  • 6
    • 84886447961 scopus 로고    scopus 로고
    • CMOS Devices below 0.1 μm: How High Will Performance Go?
    • Y. Taur and E. J. Nowak, “CMOS Devices below 0.1 μm: How High Will Performance Go?” 1997 IEDM Technical Digest, p. 215.
    • 997 IEDM Technical Digest , pp. 215
    • Taur, Y.1    Nowak, E.J.2
  • 8
    • 0031140867 scopus 로고    scopus 로고
    • Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs
    • S. -H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFETs,” IEEE Electron Device Lett., vol. 18, pp. 209-211 (1997).
    • (1997) IEEE Electron Device Lett , vol.18 , pp. 209-211
    • Lo, S.-H.1    Buchanan, D.A.2    Taur, Y.3    Wang, W.4
  • 9
    • 0001156050 scopus 로고
    • Self-Consistent Results for n-Type Si Inversion Layers
    • F. Stern, “Self-Consistent Results for n-Type Si Inversion Layers,” Physical Review B, vol. 5, no. 12, pp. 4891-4899, 1972.
    • (1972) Physical Review B , vol.5 , Issue.12 , pp. 4891-4899
    • Stern, F.1
  • 13
    • 0029207481 scopus 로고
    • Performance Trends in High-End Processors
    • G. A. Sai-Halasz, “Performance Trends in High-End Processors,” IEEE Proc., vol. 83, pp. 20-36 (1995).
    • (1995) IEEE Proc , vol.83 , pp. 20-36
    • Sai-Halasz, G.A.1
  • 14
    • 0024178927 scopus 로고    scopus 로고
    • On Universality of Inversion-Layer Mobility in n- and p-Channel MOSFETs
    • S. Takagi, M. Iwase, and A. Toriumi, “On Universality of Inversion-Layer Mobility in n- and p-Channel MOSFETs,” 1988 IEDM Technical Digest, pp. 398-401.
    • 1988 IEDM Technical Digest , pp. 398-401
    • Takagi, S.1    Iwase, M.2    Toriumi, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.