Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 11-16

  Rodriguez R ^a,b   Stathis, J H ^b   Linder, B P ^b  

^a UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

^b IBM RESEARCH   (United States)

Author keywords

CMOS; Dielectric breakdown; Hard breakdown; Leakage currents; Oxide breakdown; Oxide reliability

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN; LEAKAGE CURRENTS; STATIC RANDOM ACCESS STORAGE;

STRESS POLARITY;

ELECTRIC INVERTERS;

EID: 0037634817     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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