Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 300-305

  Carter, Jonathan R ^a   Ozev, Sule ^a   Sorin, Daniel J ^a  

^a Duke University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE FAILURES; OXIDE BREAKDOWN (OBD); PATTERN GENERATORS; TEST PATTERNS;

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; CURRENT DENSITY; ERROR DETECTION; LOGIC GATES; PROBABILITY;

GATES (TRANSISTOR);

EID: 33646899067     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.94     Document Type: Conference Paper

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