Exploiting STI stress for performance

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 83-90

  Kahng, Andrew B ^a,b   Sharma, Puneet ^b   Topaloglu, Rasit O ^a,c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM NODES; CIRCUIT PERFORMANCES; CLOCK FREQUENCIES; COMPUTER-AIDED DESIGN; CRITICAL PATHS; DELAY ANALYSIS; IMPACT MODELING; INTERNATIONAL CONFERENCES; INTRINSIC STRESSES; PERFORMANCE IMPROVEMENTS; PLACE AND ROUTE; PROCESS SIMULATIONS; PRODUCTION CELLS; SHALLOW-TRENCH ISOLATION; STANDARD-CELL DESIGNS; STRESS ENGINEERING; TIMING-DRIVEN; WIRE LENGTHS;

DESIGN; ELECTRIC BATTERIES; NETWORKS (CIRCUITS); OPTIMIZATION; SPEECH ANALYSIS; STANDARDS; TECHNOLOGY; TIME MEASUREMENT;

SEMICONDUCTING SILICON;

EID: 45849104431     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397248     Document Type: Conference Paper

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