Modeling well edge proximity effect on highly-scaled MOSFETs

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 831-834

  Sheu, Yi Ming ^a,b,c   Su, Ke Wei ^a,b   Yang, Sheng Jier ^a,b   Chen, Hsien Te ^a,b   Wang, Chih Chiang ^a,b   Chen, Ming Jer ^a,c   Liu, Sally ^a,b  

^a Hsinchu Science Park ^*  (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC FIELD EFFECTS; MATHEMATICAL MODELS;

CMOS TECHNOLOGY; EDGE PROXIMITY EFFECTS;

MOSFET DEVICES;

EID: 33846280931     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568798     Document Type: Conference Paper

References (4)

1. G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, "NMOS drive current reduction caused by transistor layout and trench isolation induced stress," in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
2. R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
3. K. W. Su, et al., "A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics," in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
4. T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, "Lateral Ion Implant Straggle and Mask Proximity Effect," IEEE Trans. Electron Devices, vol. 50, pp. 1946-1951, September 2003.