Stress management in sub-90-nm transistor architecture

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1740-1743

  Arghavani, R ^a   Yuan, Z ^a   Ingle, N ^a   Jung, K B ^a   Seamons, M ^a   Venkataraman, S ^a   Banthia, V ^a   Lilja, K ^b   Leon, P ^b   Karunasiri, G ^c   Yoon, S ^d   Mascarenhas, A ^d  

^a APPLIED MATERIALS INC   (United States)

^b Mixed Technology Associates LLC   (United States)

^c NAVAL POSTGRADUATE SCHOOL   (United States)

^d NATIONAL RENEWABLE ENERGY LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRESS; COMPUTER SIMULATION; DIELECTRIC FILMS; NITRIDES; OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; TENSILE STRESS;

SEMICONDUCTOR FILMS; SHALLOW TRENCH ISOLATION; STRESS MANAGEMENT;

TRANSISTORS;

EID: 5444249918     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.835993     Document Type: Article

References (13)

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