Stress memorization technique (SMT) optimization for 45nm CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 78-79

  Ortolland, C ^a,e   Morin, P ^b   Chaton, C ^c   Mastromatteo, E ^a   Populaire, C ^d   Orain, S ^a   Leverd, F ^b   Stolk, P ^a   Boeuf, F ^b   Arnaud, F ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

^c CEA LETI   (France)

^d FREESCALE SEMICONDUCTOR INC   (United States)

^e Lab Physique de la Matiére   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CONSUMER ELECTRONICS; GATE DIELECTRICS; MOS DEVICES; OPTIMIZATION; POLYSILICON;

NITRIDE CAPPING LAYER; STRESS MEMORIZATION TECHNIQUE (SMT);

CMOS INTEGRATED CIRCUITS;

EID: 41149150847     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2006.1705225     Document Type: Conference Paper

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