Energy awareness and uncertainty in microarchitecture-level design

IEEE Micro

Volumn 25, Issue 5, 2005, Pages 64-76

  Marculescu, Diana ^a,b   Talpes, Emil ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS;

MICROARCHITECTURE MODELING; MICROARCHITECTURE-LEVEL DESIGN; SYSTEM PARAMETER VARIABILITY;

PROGRAM PROCESSORS;

EID: 28244455768     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.86     Document Type: Article

References (14)

1. K.A. Bowman, S.G. Duvall, and J.M. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, Feb. 2002, pp. 183-190.
2. J. Tschanz et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE J. Solid-State Circuits, vol. 37, no. 11, Nov. 2002, pp. 1396-1402.
3. S. Borkar, T. Karnik, and V. De, "Design and Reliability Challenges in Nanometer Technologies," Proc. 41st Ann. ACM/IEEE Design Automation Conf. (DAC 04), ACM Press, 2004, p. 75.
4. M. Eisele et al., "The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits," IEEE Trans. Very Large Scale (VLSI) Integration Systems, vol. 5, no. 4, Dec. 1997, pp. 360-368.
5. G. Semeraro et al., "Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture," Proc. 35th Int'l Symp. Microarchitecture (Micro 35), ACM Press, 2002, pp. 356-367.
6. A. Iyer and D. Marculescu, "Power Efficiency of Multiple Clock, Multiple Voltage Cores," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 02), IEEE Press, 2002, pp. 379-386.
7. E. Talpes and D. Marculescu, "A Critical Analysis of Application-Adaptive Multiple Clock Processors," Proc. ACM/IEEE Int'l Symp. Low-Power Electronics and Design (ISLPED 03), IEEE Press, 2003, pp. 278-281.
8. K. Skadron et al., "Temperature-Aware Microarchitecture," Proc. 30th Ann. Int'l Symp. Computer Architecture, IEEE Press, 2003, pp. 2-13.
9. A. Basu et al., "Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era," Proc. 41st Ann. ACM/IEEE Design Automation Conf. (DAC 04), ACM Press, 2004, pp. 884-887.
10. S. Palacharla, N.P. Jouppi, and J.E. Smith, "Complexity-Effective Superscalar Processors," Proc. 24th Ann. Int'l Symp. Computer Architecture, IEEE Press, 1997, pp. 206-218.
11. S. McFarling, Combining Branch Predictors, tech. report DEC WRL TN-36, DEC Western Research Laboratory, 1993.
12. E. Acar et al., "Leakage and Leakage Sensitivity Computation for Combinational Circuits," Proc. ACM/IEEE Int'l Symp. Low-Power Electronics and Design (ISLPED 03), IEEE Press, 2003, pp. 96-99.
13. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A FrameworK for Architectural-Level Power Analysis and Optimizations," Proc. 27th Ann. Int'l Symp. Computer Architecture, IEEE Press, 2000, pp. 83-94.
14. J.A. Butts and G.S. Sohi, "A Static Power Model for Architects," Proc. 33rd Int'l Symp. Microarchitecture (Micro 33), ACM Press, 2000, pp. 191-201.