Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 19-23

  Narendra, Siva ^a,b   De, Vivek ^b   Borkar, Shekhar ^b   Antoniadis, Dimitri ^a   Chandrakasan, Anantha ^a  

^a USA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

CMOS; Sub threshold leakage; Within die variation

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROELECTRONICS; MICROPROCESSOR CHIPS; POWER CONTROL; SEMICONDUCTOR DEVICE MODELS; STATISTICAL METHODS; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

FULL CHIP LEAKAGE POWER; POWER DISSIPATION; SUBTHRESHOLD LEAKAGE POWER;

POWER ELECTRONICS;

EID: 0036949325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/566412.566415     Document Type: Conference Paper

References (13)

1. V. De and S. Borkar, "Technology and Design Challenges for Low Power & High Performance," Intl. Symp. Low Power Electronics and Design, pp. 163-168, Aug. 1999.
2. A. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-Power CMOS Digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992.
3. D. Antoniadis and J.E. Chung, "Physics and Technology of Ultra Short Channel MOSFET Devices," Intl. Electron devices Meeting, pp. 21-24, 1991.
4. Z. Chen, J. Shott, J. Burr, and J. D. Plummer, "CMOS Technology Scaling for Low Voltage Low Power Applications," IEEE Symp. Low Power Elec., pp. 56-57, 1994.
5. H.C. Poon, L.D. Yu, R.L. Johnston, D. Beecham, "DC Model for Short-Channel IGFET's," IEEE Intl. Electron Devices Meeting, pp. 156-159, Dec. 1973.
6. S. W. Sun and P. G. Y. Tsui, "Limitation of Supply Voltage Scaling by MOSFET Threshold-Voltage variation," IEEE Custom Integrated Circuits Conf., pp. 267-270, 1994.
7. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.
8. D.A. Muller, T. Sorsch, S. Moccio, F.H. Baumann, K. Evans-Lutterodt, and G. Timp, "The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides," Nature, vol. 399, pp. 758-761, June 1999.
9. M. Schulz, "The End of the Road for Silicon," Nature, vol. 399, pp. 729-730, June 1999.
10. K. Reid, B. Taylor, L. Dip, L. Herbert, R. Garcia, R. Hegde, J. Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, B. Nguyen, and P. Tobin, "80 nm Poly-Si Gate CMOS with HfO2 Gate Dielectric," IEEE Intl. Electron Devices Meeting, Paper 30.1, Dec. 2001.
11. J. Lee, G. Tarachi, A. Wei, T. A. Langdo, E. A. Fitzgerald, D. Antoniadis, "Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy," Intl. Electron Devices Meeting, pp. 71-74, 1999.
12. I. Kohno, T. Sano, N. Katoh, and K. Yano, "Threshold Canceling Logic (TCL): A Post-CMOS Logic Family Scalable Down to 0.02 μm," Intl. Solid-State Circuits Conf., pp. 218-219, 2000.
13. A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, V. De, "Effectiveness of reverse body bias for leakage control, in scaled dual Vt CMOS ICs," Intl. Symp. Low Power Electronics and Design, pp. 207-212, Aug. 2001.