A 5.1GHz 0.34mm2router for network-on-chip applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 42-43

  Vangal, Srirarn ^a,b   Singh, Arvind ^a   Howard, Jason ^a   Dighe, Saurabh ^a   Borkar, Nitin ^a   Alvandpour, Atila ^b  

^a INTEL CORPORATION   (United States)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; NETWORK ARCHITECTURE; PACKET NETWORKS; PIPELINE PROCESSING SYSTEMS; TRANSISTORS;

COMMUNICATION FABRIC; CROSSBAR ARCHITECTURE; NETWORK-ON-CHIP (NOC) ARCHITECTURE; ROUTER LAYOUT;

ROUTERS;

EID: 39749130315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342758     Document Type: Conference Paper

References (4)

1. S. Varigal et al., "Ail SO-Tile 1.2STFLOPS Nctwork-on-Chip in 65nm CMOS, " ISSCC Dig. Tech. Papers, pp. 98-99, Feb. 2007.
2. H. Wilson et al., IEEE JSSC, pp. 1954-1963, Dec. 2001.
3. [31 F. Klass 1998 Symposium on VLSI Circuits, pp. 108-109.
4. P. Bai et al., IEDM technical digest, pp. 657-660, 2004.