Multilevel circuit partitioning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 8, 1998, Pages 655-667

  Alpert, Charles J ^a   Huang, Jen Hsin ^a,b   Kahng, Andrew B ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Optimization; Partitioning; Physical design; Placement

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; ITERATIVE METHODS; OPTIMIZATION;

MULTILEVEL CIRCUIT PARTITIONING;

ELECTRIC NETWORK SYNTHESIS;

EID: 0032138427     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.712098     Document Type: Article

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