S-Tree: A technique for buffered routing tree synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 578-583

  Hrkic, Milos ^a   Lillis, John ^a  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Buffer insertion; Routing; Steiner trees; Timing optimization

Indexed keywords

ALGORITHMS; BUFFER STORAGE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; OPTIMIZATION;

BUFFERED ROUTING TREE SYNTHESIS;

TREES (MATHEMATICS);

EID: 0036048606     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2002.1012692     Document Type: Conference Paper

References (11)

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9. Buffered steiner tree construction with wire sizing for interconnect layout optimization
10. Buffer placement in distributed RC-Tree networks for minimal elmore delay
11. Simultaneous routing and buffer insertion with restrictions on buffer locations