Fast and flexible buffer trees that navigate the physical layout environment

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 24-29

  Alpert, Charles J ^a   Hrkic, Milos ^b   Hu, Jiang ^c   Quay, Stephen T ^a  

^a IBM   (United States)

^b UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^c TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Buffer insertion; Global routing; Physical synthesis

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER AIDED ENGINEERING; OPTIMIZATION; PROBLEM SOLVING; ROUTERS;

BUFFER INSERTION; BUFFER TREES; GLOBAL ROUTING; PHYSICAL SYNTHESIS;

INTEGRATED CIRCUITS;

EID: 4444327013     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996575     Document Type: Conference Paper

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