Buffer block planning for interconnect planning and prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 929-937

  Cong, Jason ^a,b   Kong, Tianming ^a,b   Pan, Zhigang ^a,c  

^a IEEE   (United States)

^b Engineering IV   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Buffer insertion and planning; Feasible region; Floorplanning; Interconnect planning and prediction

Indexed keywords

BUFFER BLOCK PLANNING (BBP);

ALGORITHMS; BUFFER STORAGE; LARGE SCALE SYSTEMS; OPTIMIZATION; SYSTEMS ANALYSIS;

VLSI CIRCUITS;

EID: 0035706051     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974906     Document Type: Article

References (31)

1. Performance optimization of VLSI interconnect layout
2. Interconnect design for deep submicron ICs
3. Global wires harmful?
4. Interconnect delay estimation models for synthesis and design planning
5. Planning for performance
6. Challenges and opportunities for design innovations in nanometer technologies
7. An interconnect-Centric design flow for nanometer technologies
8. Buffer placement in distributed RC-tree networks for minimal elmore delay
9. Optimal wire sizing and buffer insertion for low power and a generalized delay model
10. Buffered Steiner tree construction with wire sizing for interconnect layout optimization
11. Closed form solution to simultaneous buffer insertion/sizing and wire sizing
12. Hierarchical placement and floorplanning for BEAR
13. Floorplan design of VLSI circuits
14. Rectangle-packing-based module placement
15. Delay bounded buffered tree construction for timing driven floorplanning
16. An interconnect-centric design flow for nanometer technologies
17. Buffer block planning for interconnect-driven floorplanning
18. Fastcap: A multipole accelerated 3-D capacitance extraction program
19. Wire segmenting for improved buffer insertion
20. Graphs in floor-plan design
21. Relaxed simulated tempering for VLSI floorplan design
22. Planning buffer locations by network flows
23. Routability-driven repeater block planning for interconnect-centric floorplanning
24. Routability-driven repeater block planning for interconnect-centric floorplanning
25. Repeater block planning under simultaneous delay and transition time constraints
26. Provably good global buffering using an available buffer block plan
27. Provably good global buffering by multiterminal multicommodity flow approximation
28. A practical methodology for early buffer and wire resource allocation