-
1
-
-
0036377317
-
Consistent placement of macroblock using floorplanning and standard-cell placement
-
J S. N. Adya and I. L. Markov, "Consistent placement of macroblock using floorplanning and standard-cell placement," in Proc. Int. Symp. Phys. Design, 2002, pp. 12-17.
-
(2002)
Proc. Int. Symp. Phys. Design
, pp. 12-17
-
-
Adya, J.S.N.1
Markov, I.L.2
-
2
-
-
0346148463
-
On whitespace in mixed-size placement and physical sysnthesis
-
S. N. Adya, I. L. Markov, and P. G. Villarrubia, "On whitespace in mixed-size placement and physical sysnthesis," in Proc. Int. Conf. Computer-Aided Design, 2003, pp. 311-318.
-
(2003)
Proc. Int. Conf. Computer-aided Design
, pp. 311-318
-
-
Adya, S.N.1
Markov, I.L.2
Villarrubia, P.G.3
-
3
-
-
0031652243
-
Faster minimization of linear wirelength for global placement
-
Jan.
-
C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, and P. Mulet, "Faster minimization of linear wirelength for global placement," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 17, no. 1, pp. 3-13, Jan. 1998.
-
(1998)
IEEE Trans. Computer-aided Design Integr. Circuits Syst.
, vol.17
, Issue.1
, pp. 3-13
-
-
Alpert, C.J.1
Chan, T.2
Kahng, A.B.3
Markov, I.4
Mulet, P.5
-
4
-
-
0030646148
-
Multilevel circuit partitioning
-
C. J. Alpert, J.-H. Huang, and A. B. Kahng, "Multilevel circuit partitioning," in Proc. Design Automation Conf., 1997, pp. 530-533.
-
(1997)
Proc. Design Automation Conf.
, pp. 530-533
-
-
Alpert, C.J.1
Huang, J.-H.2
Kahng, A.B.3
-
5
-
-
0036907219
-
Free space management for cut-based placement
-
Nov.
-
C. J. Alpert, G.-J. Nam, and P. G. Villarrubia, "Free space management for cut-based placement," in Proc. Int. Conf. Computer Aided Design, Nov. 2002, pp. 746-751.
-
(2002)
Proc. Int. Conf. Computer Aided Design
, pp. 746-751
-
-
Alpert, C.J.1
Nam, G.-J.2
Villarrubia, P.G.3
-
6
-
-
0009790428
-
Function smoothing with applications to VLSI layout
-
Jan.
-
R. Baldick, A. B. Kahng, A. Kennings, and I. L. Markov, "Function smoothing with applications to VLSI layout," in Proc. Asia South Pacific Design Automation Conf., Jan. 1999, pp. 225-228.
-
(1999)
Proc. Asia South Pacific Design Automation Conf.
, pp. 225-228
-
-
Baldick, R.1
Kahng, A.B.2
Kennings, A.3
Markov, I.L.4
-
7
-
-
0032651060
-
Hypergraph partitioning for VLSI CAD: Methodology for reporting, and new results
-
Jun.
-
A. E. Caldwell, A. B. Kahng, A. A. Kennings, and I. L. Markov, "Hypergraph partitioning for VLSI CAD: Methodology for reporting, and new results," in Proc. Design Automation Conf., Jun. 1999, pp. 349-354.
-
(1999)
Proc. Design Automation Conf.
, pp. 349-354
-
-
Caldwell, A.E.1
Kahng, A.B.2
Kennings, A.A.3
Markov, I.L.4
-
8
-
-
0033697586
-
Can recursive bisection alone produce routable placements?
-
A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Can recursive bisection alone produce routable placements?," in Proc. Design Automation Conf., 2000, pp. 477-482.
-
(2000)
Proc. Design Automation Conf.
, pp. 477-482
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
9
-
-
84886477330
-
Implications of area-array I/O for row-based placement methodology
-
Feb.
-
A. E. Caldwell, A. B. Kahng, S. Mantik, and I. L. Markov, "Implications of area-array I/O for row-based placement methodology," in Proc. IEEE Symp. IC/Package Design Integr., Feb. 1998, pp. 93-98.
-
(1998)
Proc. IEEE Symp. IC/Package Design Integr.
, pp. 93-98
-
-
Caldwell, A.E.1
Kahng, A.B.2
Mantik, S.3
Markov, I.L.4
-
11
-
-
84954416950
-
Multi-level placement for large-scale mixed-size IC designs
-
C. C. Chang, J. Cong, and X. Yuan, "Multi-level placement for large-scale mixed-size IC designs," in Proc. Asia South Pacific Design Automation Conf., 2003, pp. 325-330.
-
(2003)
Proc. Asia South Pacific Design Automation Conf.
, pp. 325-330
-
-
Chang, C.C.1
Cong, J.2
Yuan, X.3
-
12
-
-
0034481127
-
Potential slack: An effective metric of combinational circuit performance
-
C. Chen, X. Yang, and M. Sarrafzadeh, "Potential slack: An effective metric of combinational circuit performance," in Proc. Int. Conf. Computer-Aided Design, 2000, pp. 198-201.
-
(2000)
Proc. Int. Conf. Computer-aided Design
, pp. 198-201
-
-
Chen, C.1
Yang, X.2
Sarrafzadeh, M.3
-
13
-
-
0034818786
-
A performance-driven standard cell placer based on a modified force-directed algorithm
-
Y.-C. Chou and Y.-L. Lin, "A performance-driven standard cell placer based on a modified force-directed algorithm," in Proc. Int. Symp. Physical Design, 2001, pp. 24-29.
-
(2001)
Proc. Int. Symp. Physical Design
, pp. 24-29
-
-
Chou, Y.-C.1
Lin, Y.-L.2
-
14
-
-
18744383484
-
-
[Online]
-
Dragon [Online]. Available: http://er.cs.ucla.edu/Dragon/
-
-
-
-
17
-
-
0033348302
-
Attractor-repeller approach for global placement
-
H. Etawil, S. Areibi, and A. Vannelli, "Attractor-repeller approach for global placement," in Proc. Int. Conf. Computer-Aided Design, 1999, pp. 20-24.
-
(1999)
Proc. Int. Conf. Computer-aided Design
, pp. 20-24
-
-
Etawil, H.1
Areibi, S.2
Vannelli, A.3
-
18
-
-
0027872967
-
A performance driven hierarchical partitioning placement algorithm
-
Sep.
-
T. Gao, C. L. Liu, and K. C. Chen, "A performance driven hierarchical partitioning placement algorithm," in Proc. Eur. Design Automation Conf., Sep. 1993, pp. 33-38.
-
(1993)
Proc. Eur. Design Automation Conf.
, pp. 33-38
-
-
Gao, T.1
Liu, C.L.2
Chen, K.C.3
-
19
-
-
0010313569
-
-
[Online]
-
VLSI CAD Bookshelf [Online]. Available: http://www.gigascale.org/ bookshelf/
-
VLSI CAD Bookshelf
-
-
-
20
-
-
0034841992
-
Timing driven placement using physical net constraints
-
B. Halpin, C.-Y. R. Chen, and N. Sehgal, "Timing driven placement using physical net constraints," in Proc. Design Automation Conf., 2001, pp. 780-783.
-
(2001)
Proc. Design Automation Conf.
, pp. 780-783
-
-
Halpin, B.1
Chen, C.-Y.R.2
Sehgal, N.3
-
21
-
-
0027316516
-
Prime: A timing-driven placement tool using a piecewise linear resistive network approach
-
T. Hamada, C. K. Cheng, and P. M Chau, "Prime: A timing-driven placement tool using a piecewise linear resistive network approach," in Proc. Design Automation Conf., 1993, pp. 531-536.
-
(1993)
Proc. Design Automation Conf.
, pp. 531-536
-
-
Hamada, T.1
Cheng, C.K.2
Chau, P.M.3
-
23
-
-
0030646008
-
Partitioning-based standard cell global placement with an exact objective
-
D. J. Huang and A. B. Kahng, "Partitioning-based standard cell global placement with an exact objective," in Proc. Int. Symp. Phys. Design, 1997, pp. 18-25.
-
(1997)
Proc. Int. Symp. Phys. Design
, pp. 18-25
-
-
Huang, D.J.1
Kahng, A.B.2
-
24
-
-
0036377280
-
FAR: Fixed-points addition & relaxation based placement
-
B. Hu and M. Marek-Sadowska, "FAR: Fixed-points addition & relaxation based placement," in Proc. Int. Symp. Phys. Design, 2002, pp. 161-166.
-
(2002)
Proc. Int. Symp. Phys. Design
, pp. 161-166
-
-
Hu, B.1
Marek-Sadowska, M.2
-
25
-
-
18744394777
-
-
[Online]
-
IBM-PLACE 2.0 Benchmark Suites [Online]. Available: http://er.cs.ucla. edu/benchmarks/ibm-place2/
-
-
-
-
27
-
-
18744373463
-
-
[Online]
-
ISPD 2001 Circuit Benchmarks [Online]. Available: http://nthucad.cs.nthu. edu.tw/~ycchou/benchmark/placement.htm
-
ISPD 2001 Circuit Benchmarks
-
-
-
28
-
-
0024911063
-
Performance-driven placement of cell based IC's
-
M. Jackson and E. S. Kuh, "Performance-driven placement of cell based IC's," in Proc. Design Automation Conf., 1989, pp. 370-375.
-
(1989)
Proc. Design Automation Conf.
, pp. 370-375
-
-
Jackson, M.1
Kuh, E.S.2
-
29
-
-
2942682815
-
Implementation and extensibility of an analytic placer
-
A. B. Kahng and Q. Wang, "Implementation and extensibility of an analytic placer," in Proc. Int. Symp. Phys. Design, 2004, pp. 18-25.
-
(2004)
Proc. Int. Symp. Phys. Design
, pp. 18-25
-
-
Kahng, A.B.1
Wang, Q.2
-
30
-
-
16244391451
-
An analytic placer for mixed-size placement and timing-driven placement
-
_, "An analytic placer for mixed-size placement and timing-driven placement," in Proc. Int. Conf. Computer Aided Design, 2004, pp. 565-572.
-
(2004)
Proc. Int. Conf. Computer Aided Design
, pp. 565-572
-
-
-
32
-
-
0030686036
-
Multilevel hypergraph partitioning: Applications in VLSI design
-
G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: Applications in VLSI design," in Proc. Design Automation Conf., 1997, pp. 526-529.
-
(1997)
Proc. Design Automation Conf.
, pp. 526-529
-
-
Karypis, G.1
Aggarwal, R.2
Kumar, V.3
Shekhar, S.4
-
33
-
-
0036311655
-
Smoothening max-terms and analytical minimization of half-perimeter wirelength
-
A. A. Kennings and I. L. Markov, "Smoothening max-terms and analytical minimization of half-perimeter wirelength," VLSI Design, vol. 14, no. 3, pp. 229-237, 2002.
-
(2002)
VLSI Design
, vol.14
, Issue.3
, pp. 229-237
-
-
Kennings, A.A.1
Markov, I.L.2
-
35
-
-
2942639676
-
Recursive bisection based mixed block placement
-
A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, and P. H. Madden, "Recursive bisection based mixed block placement," in Proc. Int. Symp. Phys. Design, 2004, pp. 84-89.
-
(2004)
Proc. Int. Symp. Phys. Design
, pp. 84-89
-
-
Khatkhate, A.1
Li, C.2
Agnihotri, A.R.3
Yildiz, M.C.4
Ono, S.5
Koh, C.-K.6
Madden, P.H.7
-
36
-
-
0346238015
-
A novel net weighting algorithm for timing-driven placement
-
T. Kong, "A novel net weighting algorithm for timing-driven placement," in Proc. Int. Conf. Computer-Aided Design, 2002, pp. 10-14.
-
(2002)
Proc. Int. Conf. Computer-aided Design
, pp. 10-14
-
-
Kong, T.1
-
37
-
-
0026131224
-
GORDIAN: VLSI placement by quadratic programming and slicing optimization
-
Mar.
-
J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 10, no. 3, pp. 356-365, Mar. 1991.
-
(1991)
IEEE Trans. Computer-aided Design Integr. Circuits Syst.
, vol.10
, Issue.3
, pp. 356-365
-
-
Kleinhans, J.1
Sigl, G.2
Johannes, F.3
Antreich, K.4
-
38
-
-
0029695151
-
New spectral linear placement and clustering approach
-
J.-M. Li, J. Lillis, L.-T. Liu, and C.-K. Cheng, "New spectral linear placement and clustering approach," in Proc. Design Automation Conf., 1996, pp. 88-93.
-
(1996)
Proc. Design Automation Conf.
, pp. 88-93
-
-
Li, J.-M.1
Lillis, J.2
Liu, L.-T.3
Cheng, C.-K.4
-
39
-
-
0029542930
-
Linear decomposition algorithm for VLSI design applications
-
J.-M. Li, J. Lillis, and C.-K. Cheng, "Linear decomposition algorithm for VLSI design applications," in Proc. Int. Conf. Computer-Aided Design, 1995, pp. 223-228.
-
(1995)
Proc. Int. Conf. Computer-aided Design
, pp. 223-228
-
-
Li, J.-M.1
Lillis, J.2
Cheng, C.-K.3
-
40
-
-
2942649186
-
On improving recursive bipartitioning-based placement
-
Purdue Univ., West Lafayette, IN
-
C. Li and C.-K. Koh, "On Improving Recursive Bipartitioning-Based Placement," Purdue Univ., West Lafayette, IN, Tech. Rep. TR-ECE-03-14, 2003.
-
(2003)
Tech. Rep.
, vol.TR-ECE-03-14
-
-
Li, C.1
Koh, C.-K.2
-
41
-
-
0033723218
-
Timing-driven placement for FPGAs
-
A. Marquardt, V. Betz, and J. Rose, "Timing-driven placement for FPGAs," in Proc. ACM Symp. FPGAs, 2000, pp. 203-213.
-
(2000)
Proc. ACM Symp. FPGAs
, pp. 203-213
-
-
Marquardt, A.1
Betz, V.2
Rose, J.3
-
43
-
-
0024716080
-
Generation of performance constraints for layout
-
Aug.
-
R. Nair, C. L. Berman, P. Hauge, and E. J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 8, no. 8, pp. 860-874, Aug. 1989.
-
(1989)
IEEE Trans. Computer-aided Design Integr. Circuits Syst.
, vol.8
, Issue.8
, pp. 860-874
-
-
Nair, R.1
Berman, C.L.2
Hauge, P.3
Yoffa, E.J.4
-
45
-
-
0033712214
-
Timing-driven placement based on partitioning with dynamic cut-net control
-
S.-L. Ou and M. Pedram, "Timing-driven placement based on partitioning with dynamic cut-net control," in Proc. Design Automation Conf., 2000, pp. 472-476.
-
(2000)
Proc. Design Automation Conf.
, pp. 472-476
-
-
Ou, S.-L.1
Pedram, M.2
-
46
-
-
0038379147
-
Timing driven force directed placement with physical net constraints
-
K. Rajagopal, T. Shaked, Y. Parasuram, T. Cao, A. Chowdhary, and B. Halpin, "Timing driven force directed placement with physical net constraints," in Proc. Int. Symp. Phys. Design, 2003, pp. 60-66.
-
(2003)
Proc. Int. Symp. Phys. Design
, pp. 60-66
-
-
Rajagopal, K.1
Shaked, T.2
Parasuram, Y.3
Cao, T.4
Chowdhary, A.5
Halpin, B.6
-
47
-
-
0027067732
-
RITUAL: A performance driven placement for small-cell ICs
-
A. Srinivasan, K. Chaudhary, and E. S. Kuh, "RITUAL: A performance driven placement for small-cell ICs," in Proc. Int. Conf. Computer-Aided Design, 1991, pp. 48-51.
-
(1991)
Proc. Int. Conf. Computer-aided Design
, pp. 48-51
-
-
Srinivasan, A.1
Chaudhary, K.2
Kuh, E.S.3
-
48
-
-
0029226969
-
Timing driven placement for large standard cell circuits
-
W. Swartz and C. Sechen, "Timing driven placement for large standard cell circuits," in Proc. Design Automation Conf., 1995, pp. 211-215.
-
(1995)
Proc. Design Automation Conf.
, pp. 211-215
-
-
Swartz, W.1
Sechen, C.2
-
49
-
-
0026175786
-
An analytic net weighting approach for performance optimization in circuit placement
-
R. S. Tsay and J. Koehl, "An analytic net weighting approach for performance optimization in circuit placement," in Proc. Design Automation Conf., 1991, pp. 620-625.
-
(1991)
Proc. Design Automation Conf.
, pp. 620-625
-
-
Tsay, R.S.1
Koehl, J.2
-
51
-
-
0026174925
-
Analytical placement: A linear or a quadratic objective function?
-
G. Sigl, K. Doll, and F. M. Johannes, "Analytical placement: A linear or a quadratic objective function?," in Proc. Design Automation Conf., 1991, pp. 427-431.
-
(1991)
Proc. Design Automation Conf.
, pp. 427-431
-
-
Sigl, G.1
Doll, K.2
Johannes, F.M.3
-
52
-
-
0029264395
-
Efficient and effective placement for very large circuits
-
Mar.
-
W.-J. Sun and C. Sechen, "Efficient and effective placement for very large circuits," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 14, no. 3, pp. 349-359, Mar. 1995.
-
(1995)
IEEE Trans. Computer-aided Design Integr. Circuits Syst.
, vol.14
, Issue.3
, pp. 349-359
-
-
Sun, W.-J.1
Sechen, C.2
-
53
-
-
0024125597
-
PROUD: A sea-of-gates placement algorithm
-
Dec.
-
R. S. Tsay, E. Kuh, and C. P. Hsu, "PROUD: A sea-of-gates placement algorithm," IEEE Design Test Comput., vol. 5, no. 6, pp. 44-56, Dec. 1988.
-
(1988)
IEEE Design Test Comput.
, vol.5
, Issue.6
, pp. 44-56
-
-
Tsay, R.S.1
Kuh, E.2
Hsu, C.P.3
-
54
-
-
0024890267
-
IBM RISC chip design methodology
-
P. Villarrubia, G. Nusbaum, R. Masleid, and P. T. Patel, "IBM RISC chip design methodology," in Proc. Int. Conf. Comput. Design, 1989, pp. 143-147.
-
(1989)
Proc. Int. Conf. Comput. Design
, pp. 143-147
-
-
Villarrubia, P.1
Nusbaum, G.2
Masleid, R.3
Patel, P.T.4
-
55
-
-
2942639682
-
FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
-
N. Viswanathan and C. C.-N. Chu, "FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model," in Proc. Int. Symp. Phys. Design, 2004, pp. 26-33.
-
(2004)
Proc. Int. Symp. Phys. Design
, pp. 26-33
-
-
Viswanathan, N.1
Chu, C.C.-N.2
-
56
-
-
0030718152
-
Algorithms for large-scale fiat placement
-
J. Vygen, "Algorithms for large-scale fiat placement," in Proc. Design Automation Conf., 1997, pp. 746-751.
-
(1997)
Proc. Design Automation Conf.
, pp. 746-751
-
-
Vygen, J.1
-
57
-
-
0036395443
-
A standard-cell placement tool for designs with high row utilization
-
Sep.
-
X. Yang, B.-K. Choi, and M. Sarrafzadeh, "A standard-cell placement tool for designs with high row utilization," in Proc. Int. Conf. Comput. Design, Sep. 2002, pp. 45-47.
-
(2002)
Proc. Int. Conf. Comput. Design
, pp. 45-47
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
-
58
-
-
0036375950
-
Routability driven white space allocation for fixed-die standard-cell placement
-
_, "Routability driven white space allocation for fixed-die standard-cell placement," in Proc. Int. Symp. Phys. Design, 2002, pp. 42-47.
-
(2002)
Proc. Int. Symp. Phys. Design
, pp. 42-47
-
-
-
59
-
-
0036916522
-
Timing-driven placement using design hierarchy guided constraint
-
X. Yang, B.-K. Choi, and M. Sarrafzadeh, "Timing-driven placement using design hierarchy guided constraint," in Proc. Int. Conf. Computer-Aided Design, 2002, pp. 177-180.
-
(2002)
Proc. Int. Conf. Computer-aided Design
, pp. 177-180
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
-
60
-
-
0034841571
-
Improved cut sequences for partitioning based placement
-
M. C. Yildiz and P. H. Madden, "Improved cut sequences for partitioning based placement," in Proc. Design Automation Conf., 2001, pp. 776-779.
-
(2001)
Proc. Design Automation Conf.
, pp. 776-779
-
-
Yildiz, M.C.1
Madden, P.H.2
|