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Volumn , Issue , 2004, Pages 609-614

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER COST MINIMIZATION PROBLEMS; OPTIMAL BUFFER INSERTION; WIRE SIZING;

EID: 2442496236     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (27)

References (15)
  • 1
    • 0030697661 scopus 로고    scopus 로고
    • Wire segmenting for improved buffer insertion
    • C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," Proc. 1997 DAC, 588-593.
    • Proc. 1997 DAC , pp. 588-593
    • Alpert, C.J.1    Devgan, A.2
  • 2
    • 0031619501 scopus 로고    scopus 로고
    • Buffer insertion for noise and delay optimization
    • C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion for noise and delay optimization," Proc. 1998 DAC, 362-367.
    • Proc. 1998 DAC , pp. 362-367
    • Alpert, C.J.1    Devgan, A.2    Quay, S.T.3
  • 3
    • 0032650596 scopus 로고    scopus 로고
    • Buffer insertion with accurate gate and interconnect delay computation
    • C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion with accurate gate and interconnect delay computation," Proc. 1999 DAC, 479-484.
    • Proc. 1999 DAC , pp. 479-484
    • Alpert, C.J.1    Devgan, A.2    Quay, S.T.3
  • 4
    • 0032690813 scopus 로고    scopus 로고
    • Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment matching
    • C.-P. Chen and N. Menezes, "Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment matching," Proc. 1999 DAC, 502-506.
    • Proc. 1999 DAC , pp. 502-506
    • Chen, C.-P.1    Menezes, N.2
  • 6
    • 0036048606 scopus 로고    scopus 로고
    • S-tree: A technique for buffered routing tree synthesis
    • M. Hrkic and J. Lillis, "S-tree: a technique for buffered routing tree synthesis," Proc. 2002 DAC, 578-583.
    • Proc. 2002 DAC , pp. 578-583
    • Hrkic, M.1    Lillis, J.2
  • 8
    • 0030110490 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
    • J. Lillis, C. K. Cheng and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Trans. Solid-State Circuits, 31(3), 1996, 437-447.
    • (1996) IEEE Trans. Solid-state Circuits , vol.31 , Issue.3 , pp. 437-447
    • Lillis, J.1    Cheng, C.K.2    Lin, T.-T.Y.3
  • 10
    • 0030410359 scopus 로고    scopus 로고
    • Buffered Steiner tree construction with wire sizing for interconnect layout optimization
    • T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," Proc. 1996 ICCAD, 44-49.
    • Proc. 1996 ICCAD , pp. 44-49
    • Okamoto, T.1    Cong, J.2
  • 12
    • 0041633712 scopus 로고    scopus 로고
    • An O(n log n) time algorithm for optimal buffer insertion
    • W. Shi and Z. Li, "An O(n log n) time algorithm for optimal buffer insertion," Proc. 2003 DAC, 580-585.
    • Proc. 2003 DAC , pp. 580-585
    • Shi, W.1    Li, Z.2
  • 14
    • 0025594311 scopus 로고    scopus 로고
    • Buffer placement in distributed RC-tree network for minimal Elmore delay
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree network for minimal Elmore delay," Proc. 1990 ISCAS, 865-868.
    • Proc. 1990 ISCAS , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 15
    • 0034229328 scopus 로고    scopus 로고
    • Simultaneous routing and buffer insertion with restrictions on buffer locations
    • H. Zhou, D. F. Wong, I. M. Liu and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," IEEE Trans. Computer-Aided Design, 19(7), 2000, 819-824.
    • (2000) IEEE Trans. Computer-aided Design , vol.19 , Issue.7 , pp. 819-824
    • Zhou, H.1    Wong, D.F.2    Liu, I.M.3    Aziz, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.